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This commit is contained in:
tzim 2019-09-07 00:36:22 +02:00
parent 06cd56465f
commit a5040628a9
5 changed files with 217 additions and 286 deletions
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2
Makefile
View file

@ -54,7 +54,7 @@ RESETPORT = /dev/ttyU0
TARGET = pyrorf TARGET = pyrorf
SRC = main.c lcd.c spi.c SRC = main.c lcd.c spi.c rf24.c
CXXSRC = CXXSRC =
ASRC = i2cmaster.S ASRC = i2cmaster.S
MCU = atmega2560 MCU = atmega2560

7
lcd.c
View file

@ -20,8 +20,8 @@ uint8_t _Bl = 0x08;
uint8_t _BackliteOn = false; uint8_t _BackliteOn = false;
uint8_t _displaymode; uint8_t _displaymode=0;
uint8_t _displaycontrol; uint8_t _displaycontrol=0;
void i2csend(uint8_t data){ void i2csend(uint8_t data){
i2c_start(0x27<<1); i2c_start(0x27<<1);
@ -101,6 +101,9 @@ void lcd_init(uint8_t cols, uint8_t lines)
command(LCD_FUNCTIONSET | LCD_2LINE | LCD_5x8DOTS | LCD_4BITMODE); command(LCD_FUNCTIONSET | LCD_2LINE | LCD_5x8DOTS | LCD_4BITMODE);
_displaymode = LCD_ENTRYLEFT;
command(LCD_ENTRYMODESET | _displaymode);
} }
void lcd_clear() void lcd_clear()

19
main.c
View file

@ -18,12 +18,24 @@ void lcdprint( char* ptr){
while (*ptr) lcd_write(*ptr++); while (*ptr) lcd_write(*ptr++);
} }
void debughex (char* ptr,uint8_t len) {
while (len--) {
uint8_t c = *(ptr++);
uint8_t ch= c>>4;
c &= 0x0F;
lcd_write(ch>9?ch+'A'-10:ch+'0');
lcd_write(c>9?c+'A'-10:c+'0');
}
}
int main(void) int main(void)
{ {
bitSet(DDRB,7); bitSet(DDRB,7);
lcd_init(20,4); lcd_init(20,4);
lcd_clear(); lcd_clear();
_delay_ms(1000); _delay_ms(1000);
lcd_home(); lcd_home();
lcd_display(); lcd_display();
lcdprint("PyRO RF !"); lcdprint("PyRO RF !");
@ -33,17 +45,18 @@ int main(void)
lcd_backlight(1); lcd_backlight(1);
lcd_display(); lcd_display();
_delay_ms(3000); _delay_ms(3000);
lcd_backlight(0); //lcd_backlight(0);
lcd_display(); lcd_display();
while (1){ while (1){
lcd_setCursor(0,3); lcd_setCursor(0,3);
lcdprint("Arnaud HOUDELETTE"); lcdprint("Arnaud HOUDELETTE");
_delay_ms(3000); _delay_ms(1000);
lcd_setCursor(0,3); lcd_setCursor(0,3);
lcdprint("Emmanuel LANGLOIS"); lcdprint("Emmanuel LANGLOIS");
_delay_ms(3000); _delay_ms(1000);
} }
} }

394
rf24.c
View file

@ -1,28 +1,28 @@
#include "rf24.h" #include "rf24.h"
#include "spi.h"
#include <unistd.h>
#include <string.h>
#include <util/delay.h> #include <util/delay.h>
uint8_t PTX=0; uint8_t rf24_buffer[33];
uint8_t rf24_CONFIG = _BV(EN_CRC) | _BV(CRCO);
uint8_t rf24_EN_AA = 0x3F; //ENAA_P0 - ENAA_P5
uint8_t rf24_EN_RXADDR = _BV(ERX_P0)|_BV(ERX_P1);
uint8_t rf24_SETUP_AW = 0x03; // 5 bytes addresses
uint8_t rf24_SETUP_RETR = 0x03;
uint8_t rf24_RF_CH = 0x02; // Channel
uint8_t rf24_RF_SETUP = _BV(RF_DR_HIGH) | _BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH);
uint8_t rf24_FEATURE = 0;
uint8_t rf24_DYNPD= 0;
uint8_t rf24_RX_PW[6] = { 32,32,0,0,0,0 };
uint8_t plens[]={24,12,12,12,12,12};
uint8_t lenregs[]={RX_PW_P0,RX_PW_P1,RX_PW_P2,RX_PW_P3,RX_PW_P4,RX_PW_P5};
uint8_t rf24_CONFIG = 0;
uint8_t rf24_status;
uint8_t rf24_fifo;
uint8_t rf24_addr_P0[]={ 0xE7, 0xE7, 0xE7, 0xE7, 0xE7 };
uint8_t rf24_addr_P1[]={ 0xC2, 0xC2, 0xC2, 0xC2, 0xC1 };
void inline rf24_ceHi(){ void inline rf24_ceHi(){
//CE_PIN_PORT |= _BV(CE_PIN_BIT); CE_PIN_PORT |= _BV(CE_PIN_BIT);
} }
void inline rf24_ceLow(){ void inline rf24_ceLow(){
//CE_PIN_PORT &= ~_BV(CE_PIN_BIT); CE_PIN_PORT &= ~_BV(CE_PIN_BIT);
} }
void inline rf24_csnHi(){ void inline rf24_csnHi(){
@ -33,238 +33,148 @@ void inline rf24_csnLow(){
CSN_PIN_PORT &= ~_BV(CSN_PIN_BIT); CSN_PIN_PORT &= ~_BV(CSN_PIN_BIT);
} }
void rf24_spi_transfer(uint8_t const *tx, uint8_t *rx, size_t len){
rf24_csnLow();
while(len--) *(rx++)=spi_transfer(*(tx++));
rf24_csnHi();
}
void rf24_write_lreg(const uint8_t reg, const uint8_t * val, size_t len)
{
rf24_csnLow();
spi_transfer(W_REGISTER | reg);
while(len--) spi_transfer(*(val++));
rf24_csnHi();
}
void rf24_write_reg(const uint8_t reg, const uint8_t val)
{
rf24_csnLow();
spi_transfer(W_REGISTER | reg);
spi_transfer(val);
rf24_csnHi();
}
uint8_t rf24_read_reg(const uint8_t reg)
{
rf24_csnLow();
spi_transfer(R_REGISTER | reg);
uint8_t ret = spi_transfer(0);
rf24_csnHi();
return ret;
}
void rf24_update_fifo_status()
{
rf24_csnLow();
rf24_status = spi_transfer(FIFO_STATUS);
rf24_fifo = spi_transfer(0);
rf24_csnHi();
}
void rf24_setup()
{
CE_PIN_DDR |= _BV(CE_PIN_BIT);
CSN_PIN_DDR |= _BV(CSN_PIN_BIT);
CE_PIN_PORT &= ~_BV(CE_PIN_BIT);
CSN_PIN_PORT |= _BV(CSN_PIN_BIT);
}
void rf24_init() void rf24_init()
{ {
//CE_PIN_DDR |= _BV(CE_PIN_BIT); rf24_write_reg(CONFIG,rf24_CONFIG);
CSN_PIN_DDR |= _BV(CSN_PIN_BIT); rf24_write_reg(EN_AA,0);
rf24_write_reg(EN_RXADDR,0x3F);
rf24_ceLow(); rf24_write_reg(SETUP_AW,0x03);
rf24_csnHi(); rf24_write_reg(SETUP_RETR,0x00);
rf24_write_reg(RF_CH,90);
// Initialize spi module rf24_write_reg(RF_SETUP,(1<<RF_DR_LOW)|(1<<RF_PWR_HIGH)|(1<<RF_PWR_LOW));
spi_begin(); rf24_write_reg(OBSERVE_TX,0);
_delay_ms(2); rf24_write_reg(RPD,0);
rf24_configure(); rf24_write_lreg(RX_ADDR_P0,rf24_addr_P0,5);
rf24_write_lreg(RX_ADDR_P1,rf24_addr_P1,5);
rf24_write_reg(RX_ADDR_P2,0xC2);
rf24_write_reg(RX_ADDR_P2,0xC3);
rf24_write_reg(RX_ADDR_P2,0xC4);
rf24_write_reg(RX_ADDR_P2,0xC5);
rf24_write_lreg(TX_ADDR,rf24_addr_P0,5);
rf24_write_reg(RX_PW_P0,plens[0]);
rf24_write_reg(RX_PW_P1,plens[1]);
rf24_write_reg(RX_PW_P2,plens[2]);
rf24_write_reg(RX_PW_P3,plens[3]);
rf24_write_reg(RX_PW_P4,plens[4]);
rf24_write_reg(RX_PW_P5,plens[5]);
rf24_write_reg(DYNPD,0);
rf24_write_reg(FEATURE,0);
} }
void inline rf24_transferSync(uint8_t *dataout,uint8_t *datain,uint8_t len){
uint8_t i;
for(i = 0;i < len;i++){
datain[i] = spi_transfer(dataout[i]);
}
}
void inline rf24_transmitSync(uint8_t *dataout,uint8_t len){
uint8_t i;
for(i = 0;i < len;i++){
spi_transfer(dataout[i]);
}
}
void inline rf24_configRegister(uint8_t reg, uint8_t value)
// Clocks only one byte into the given MiRF register
{
rf24_csnLow();
spi_transfer(W_REGISTER | (REGISTER_MASK & reg));
spi_transfer(value);
rf24_csnHi();
}
void inline rf24_readRegister(uint8_t reg, uint8_t * value, uint8_t len)
// Reads an array of bytes from the given start position in the MiRF registers.
{
rf24_csnLow();
spi_transfer(R_REGISTER | (REGISTER_MASK & reg));
rf24_transferSync(value,value,len);
rf24_csnHi();
}
void inline rf24_writeRegister(uint8_t reg, uint8_t * value, uint8_t len)
// Writes an array of bytes into inte the MiRF registers.
{
rf24_csnLow();
spi_transfer(W_REGISTER | (REGISTER_MASK & reg));
rf24_transmitSync(value,len);
rf24_csnHi();
}
void rf24_getData(uint8_t * data,uint8_t len)
{
rf24_csnLow(); // Pull down chip select
spi_transfer( R_RX_PAYLOAD ); // Send cmd to read rx payload
rf24_transferSync(data,data,len); // Read payload
rf24_csnHi(); // Pull up chip select
// NVI: per product spec, p 67, note c:
// "The RX_DR IRQ is asserted by a new packet arrival event. The procedure
// for handling this interrupt should be: 1) read payload through SPI,
// 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more
// payloads available in RX FIFO, 4) if there are more data in RX FIFO,
// repeat from step 1)."
// So if we're going to clear RX_DR here, we need to check the RX FIFO
// in the dataReady() function
rf24_configRegister(STATUS,(1<<RX_DR)); // Reset status register
}
uint8_t rf24_getDataDL(uint8_t * data,uint8_t len)
// Reads payload bytes into data array
{
uint8_t to_read;
rf24_csnLow(); // Pull down chip select
spi_transfer( R_RX_PL_WID ); // Send cmd to read rx payload len
to_read = spi_transfer(0); // Read payload
rf24_csnHi(); // Pull up chip select
if(len>to_read && to_read>0 ) len=to_read;
rf24_csnLow(); // Pull down chip select
spi_transfer( R_RX_PAYLOAD ); // Send cmd to read rx payload
rf24_transferSync(data,data,len); // Read payload
if(to_read!=len){
to_read-=len;
while((to_read--)>0) // read remaining
spi_transfer(0);
}
rf24_csnHi(); // Pull up chip select
// NVI: per product spec, p 67, note c:
// "The RX_DR IRQ is asserted by a new packet arrival event. The procedure
// for handling this interrupt should be: 1) read payload through SPI,
// 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more
// payloads available in RX FIFO, 4) if there are more data in RX FIFO,
// repeat from step 1)."
// So if we're going to clear RX_DR here, we need to check the RX FIFO
// in the dataReady() function
rf24_configRegister(STATUS,(1<<RX_DR)); // Reset status register
return to_read;
}
uint8_t inline rf24_dataReady()
// Checks if data is available for reading
{
// See note in getData() function - just checking RX_DR isn't good enough
uint8_t status = rf24_getStatus();
// We can short circuit on RX_DR, but if it's not set, we still need
// to check the FIFO for any pending packets
if ( status & (1 << RX_DR) ) return 1;
return !rf24_rxFifoEmpty();
}
uint8_t inline rf24_rxFifoEmpty(){
uint8_t fifoStatus;
rf24_readRegister(FIFO_STATUS,&fifoStatus,sizeof(fifoStatus));
return (fifoStatus & (1 << RX_EMPTY));
}
void rf24_send(uint8_t * value,uint8_t len)
// Sends a data package to the default address. Be sure to send the correct
// amount of bytes as configured as payload on the receiver.
{
uint8_t status;
status = rf24_getStatus();
if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
rf24_configRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
}
rf24_ceLow();
rf24_powerUpTx(); // Set to transmitter mode , Power up
rf24_csnLow(); // Pull down chip select
spi_transfer( FLUSH_TX ); // Write cmd to flush tx fifo
rf24_csnHi(); // Pull up chip select
rf24_csnLow(); // Pull down chip select
spi_transfer( W_TX_PAYLOAD ); // Write cmd to write payload
rf24_transmitSync(value,len); // Write payload
rf24_csnHi(); // Pull up chip select
rf24_ceHi(); // Start transmission
}
uint8_t inline rf24_isSending(){
uint8_t status;
if(PTX){
status = rf24_getStatus();
/* /*
* if sending successful (TX_DS) or max retries exceded (MAX_RT). void rf24_Off()
{
rf24_write_reg(CONFIG,rf24_CONFIG&0xF8);
}
void rf24_RXMode()
{
rf24_Off();
_delay_us(1000);
rf24_buffer[0]=FLUSH_RX;
spi_transfer_rf24(rf24_buffer,rf24_buffer,1);
rf24_write_reg(CONFIG,rf24_CONFIG|0x03);
}
void rf24_TXMode()
{
rf24_Off();
_delay_us(1000);
rf24_buffer[0]=FLUSH_TX;
spi_transfer_rf24(rf24_buffer,rf24_buffer,1);
rf24_write_reg(CONFIG,rf24_CONFIG|0x02);
_delay_us(1000);
}
int rf24_receive(uint8_t * buffer)
{
rf24_update_fifo_status();
if(rf24_fifo&1) return 0;
int pipe = (rf24_status & 0x0E) >> 1;
if(pipe==7) return 0;
int len = plens[pipe];
rf24_buffer[0]= R_RX_PAYLOAD;
spi_transfer_rf24(rf24_buffer,rf24_buffer,len+1);
memcpy ( buffer, rf24_buffer+1,len);
return len;
}
int rf24_send(uint8_t * buffer, int len){
if (len> 32 ) return -1;
int cpt=20000;
rf24_update_fifo_status();
while((cpt--)&&(rf24_fifo & 0x20)){
_delay_us(1);
rf24_update_fifo_status();
}
if(cpt==0 && (rf24_fifo & 0x20)) return 0;
memcpy(rf24_buffer+1,buffer,len);
rf24_buffer[0]=W_TX_PAYLOAD;
spi_transfer_rf24(rf24_buffer,rf24_buffer,plens[0]);
return plens[0];
}
int rf24_waitforTX()
{
int cpt=2000;
rf24_update_fifo_status();
while((cpt--)&&!(rf24_fifo & 0x10)){
_delay_us(1);
rf24_update_fifo_status();
}
return cpt==0;
}
*/ */
if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
return 0;
}
return 1;
}
return 0;
}
uint8_t inline rf24_getStatus(){
uint8_t rv;
rf24_csnLow();
rv=spi_transfer(NOP);
rf24_csnHi();
return rv;
}
void inline rf24_powerUpRx(){
PTX = 0;
rf24_ceLow();
rf24_configRegister(CONFIG, rf24_CONFIG | ( (1<<PWR_UP) | (1<<PRIM_RX) ) );
rf24_ceHi();
rf24_configRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
}
void inline rf24_flushRx(){
rf24_csnLow();
spi_transfer( FLUSH_RX );
rf24_csnHi();
}
void inline rf24_powerUpTx(){
PTX = 1;
rf24_configRegister(CONFIG, rf24_CONFIG | ( (1<<PWR_UP) | (0<<PRIM_RX) ) );
}
void inline rf24_powerDown(){
rf24_ceLow();
rf24_configRegister(CONFIG, rf24_CONFIG );
}
void rf24_configure(){
uint8_t data;
rf24_configRegister(CONFIG,rf24_CONFIG);
rf24_configRegister(FEATURE,rf24_FEATURE);
// Check Feature register ...
rf24_readRegister(FEATURE,&data,1);
if(rf24_FEATURE != data){ // ACTIVATE & retry
rf24_csnLow();
spi_transfer(ACTIVATE);
spi_transfer(0x73);
rf24_csnHi();
rf24_configRegister(FEATURE,rf24_FEATURE);
}
rf24_configRegister(EN_AA,rf24_EN_AA);
rf24_configRegister(EN_RXADDR,rf24_EN_RXADDR);
rf24_configRegister(SETUP_AW,rf24_SETUP_AW);
rf24_configRegister(SETUP_RETR,rf24_SETUP_RETR);
rf24_configRegister(RF_CH,rf24_RF_CH);
rf24_configRegister(RF_SETUP,rf24_RF_SETUP);
rf24_configRegister(DYNPD,rf24_DYNPD);
for(int i=0; i<6;i++)
rf24_configRegister(RX_PW_P0+i,rf24_RX_PW[i]);
}

87
rf24.h
View file

@ -1,47 +1,29 @@
#include <stdint.h>
#include <stdlib.h>
#ifndef RF24_h
#define RF24_h
#include "nRF24L01.h" #include "nRF24L01.h"
#include "spi.h"
#include <avr/io.h>
#include "defines.h"
void rf24_write_lreg(const uint8_t reg, const uint8_t * val, size_t len);
void rf24_write_reg(const uint8_t reg, const uint8_t val);
uint8_t rf24_read_reg(const uint8_t reg);
void rf24_update_fifo_status();
#ifdef __cplusplus extern uint8_t rf24_status;
extern "C"{ extern uint8_t rf24_fifo;
#endif
void rf24_init(); void rf24_init();
void rf24_configRegister(uint8_t reg, uint8_t value); /*
void rf24_readRegister(uint8_t reg, uint8_t * value, uint8_t len); void rf24_Off();
void rf24_writeRegister(uint8_t reg, uint8_t * value, uint8_t len); void rf24_RXMode();
void rf24_TXMode();
void rf24_getData(uint8_t * data,uint8_t len); int rf24_receive(uint8_t * buffer);
uint8_t rf24_getDataDL(uint8_t * data,uint8_t len); int rf24_send(uint8_t * buffer, int len);
uint8_t rf24_dataReady(); int rf24_waitforTX();
uint8_t rf24_rxFifoEmpty(); */
void rf24_send(uint8_t * value,uint8_t len);
uint8_t rf24_isSending();
uint8_t rf24_getStatus();
void rf24_powerUpRx();
void rf24_powerUpTx();
void rf24_powerDown();
void rf24_flushRx();
void rf24_configure();
extern uint8_t rf24_CONFIG;
extern uint8_t rf24_EN_AA;
extern uint8_t rf24_EN_RXADDR;
extern uint8_t rf24_SETUP_AW;
extern uint8_t rf24_SETUP_RETR;
extern uint8_t rf24_RF_CH;
extern uint8_t rf24_RF_SETUP;
extern uint8_t rf24_FEATURE;
extern uint8_t rf24_DYNPD;
extern uint8_t rf24_RX_PW[6];
#if defined (__AVR_ATtiny84__) || defined (__AVR_ATtiny84A__) #if defined (__AVR_ATtiny84__) || defined (__AVR_ATtiny84A__)
@ -63,10 +45,33 @@ extern uint8_t rf24_RX_PW[6];
#define CSN_PIN_DDR DDRC #define CSN_PIN_DDR DDRC
#define CSN_PIN_BIT PC6 #define CSN_PIN_BIT PC6
#elif defined(__AVR_ATmega32A__)
// CARTE PYRORF
#define CE_PIN_PORT PORTB
#define CE_PIN_DDR DDRB
#define CE_PIN_BIT PB0
#define CSN_PIN_PORT PORTB
#define CSN_PIN_DDR DDRB
#define CSN_PIN_BIT PB1
#elif defined(__AVR_ATmega2560__)
// ARDUINO MEGA
#define CE_PIN_PORT PORTL
#define CE_PIN_DDR DDRL
#define CE_PIN_BIT PL0
#define CSN_PIN_PORT PORTL
#define CSN_PIN_DDR DDRL
#define CSN_PIN_BIT PL1
#endif #endif
#ifdef __cplusplus
} // extern "C"
#endif #endif