From a5040628a9636fce92dcf45ff6d3d76af3229eab Mon Sep 17 00:00:00 2001 From: tzim Date: Sat, 7 Sep 2019 00:36:22 +0200 Subject: [PATCH] divers --- Makefile | 2 +- lcd.c | 7 +- main.c | 19 ++- rf24.c | 388 +++++++++++++++++++++---------------------------------- rf24.h | 87 +++++++------ 5 files changed, 217 insertions(+), 286 deletions(-) diff --git a/Makefile b/Makefile index dd39ff1..23975b9 100644 --- a/Makefile +++ b/Makefile @@ -54,7 +54,7 @@ RESETPORT = /dev/ttyU0 TARGET = pyrorf -SRC = main.c lcd.c spi.c +SRC = main.c lcd.c spi.c rf24.c CXXSRC = ASRC = i2cmaster.S MCU = atmega2560 diff --git a/lcd.c b/lcd.c index fb19d21..5819bf0 100644 --- a/lcd.c +++ b/lcd.c @@ -20,8 +20,8 @@ uint8_t _Bl = 0x08; uint8_t _BackliteOn = false; -uint8_t _displaymode; -uint8_t _displaycontrol; +uint8_t _displaymode=0; +uint8_t _displaycontrol=0; void i2csend(uint8_t data){ i2c_start(0x27<<1); @@ -101,6 +101,9 @@ void lcd_init(uint8_t cols, uint8_t lines) command(LCD_FUNCTIONSET | LCD_2LINE | LCD_5x8DOTS | LCD_4BITMODE); + _displaymode = LCD_ENTRYLEFT; + command(LCD_ENTRYMODESET | _displaymode); + } void lcd_clear() diff --git a/main.c b/main.c index d31ee39..90c2fa1 100644 --- a/main.c +++ b/main.c @@ -18,12 +18,24 @@ void lcdprint( char* ptr){ while (*ptr) lcd_write(*ptr++); } + +void debughex (char* ptr,uint8_t len) { + while (len--) { + uint8_t c = *(ptr++); + uint8_t ch= c>>4; + c &= 0x0F; + lcd_write(ch>9?ch+'A'-10:ch+'0'); + lcd_write(c>9?c+'A'-10:c+'0'); + } +} + int main(void) { bitSet(DDRB,7); lcd_init(20,4); lcd_clear(); _delay_ms(1000); + lcd_home(); lcd_display(); lcdprint("PyRO RF !"); @@ -33,17 +45,18 @@ int main(void) lcd_backlight(1); lcd_display(); _delay_ms(3000); - lcd_backlight(0); + //lcd_backlight(0); lcd_display(); while (1){ lcd_setCursor(0,3); lcdprint("Arnaud HOUDELETTE"); - _delay_ms(3000); + _delay_ms(1000); lcd_setCursor(0,3); lcdprint("Emmanuel LANGLOIS"); - _delay_ms(3000); + _delay_ms(1000); } + } diff --git a/rf24.c b/rf24.c index 69f4150..e97fa8a 100644 --- a/rf24.c +++ b/rf24.c @@ -1,28 +1,28 @@ - #include "rf24.h" +#include "spi.h" +#include +#include #include -uint8_t PTX=0; -uint8_t rf24_CONFIG = _BV(EN_CRC) | _BV(CRCO); -uint8_t rf24_EN_AA = 0x3F; //ENAA_P0 - ENAA_P5 -uint8_t rf24_EN_RXADDR = _BV(ERX_P0)|_BV(ERX_P1); -uint8_t rf24_SETUP_AW = 0x03; // 5 bytes addresses -uint8_t rf24_SETUP_RETR = 0x03; -uint8_t rf24_RF_CH = 0x02; // Channel -uint8_t rf24_RF_SETUP = _BV(RF_DR_HIGH) | _BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH); -uint8_t rf24_FEATURE = 0; -uint8_t rf24_DYNPD= 0; -uint8_t rf24_RX_PW[6] = { 32,32,0,0,0,0 }; +uint8_t rf24_buffer[33]; +uint8_t plens[]={24,12,12,12,12,12}; +uint8_t lenregs[]={RX_PW_P0,RX_PW_P1,RX_PW_P2,RX_PW_P3,RX_PW_P4,RX_PW_P5}; +uint8_t rf24_CONFIG = 0; +uint8_t rf24_status; +uint8_t rf24_fifo; + +uint8_t rf24_addr_P0[]={ 0xE7, 0xE7, 0xE7, 0xE7, 0xE7 }; +uint8_t rf24_addr_P1[]={ 0xC2, 0xC2, 0xC2, 0xC2, 0xC1 }; void inline rf24_ceHi(){ - //CE_PIN_PORT |= _BV(CE_PIN_BIT); + CE_PIN_PORT |= _BV(CE_PIN_BIT); } void inline rf24_ceLow(){ - //CE_PIN_PORT &= ~_BV(CE_PIN_BIT); + CE_PIN_PORT &= ~_BV(CE_PIN_BIT); } void inline rf24_csnHi(){ @@ -33,238 +33,148 @@ void inline rf24_csnLow(){ CSN_PIN_PORT &= ~_BV(CSN_PIN_BIT); } + +void rf24_spi_transfer(uint8_t const *tx, uint8_t *rx, size_t len){ + rf24_csnLow(); + while(len--) *(rx++)=spi_transfer(*(tx++)); + rf24_csnHi(); +} + +void rf24_write_lreg(const uint8_t reg, const uint8_t * val, size_t len) +{ + rf24_csnLow(); + spi_transfer(W_REGISTER | reg); + while(len--) spi_transfer(*(val++)); + rf24_csnHi(); +} + +void rf24_write_reg(const uint8_t reg, const uint8_t val) +{ + rf24_csnLow(); + spi_transfer(W_REGISTER | reg); + spi_transfer(val); + rf24_csnHi(); +} + +uint8_t rf24_read_reg(const uint8_t reg) +{ + rf24_csnLow(); + spi_transfer(R_REGISTER | reg); + uint8_t ret = spi_transfer(0); + rf24_csnHi(); + return ret; +} + +void rf24_update_fifo_status() +{ + rf24_csnLow(); + rf24_status = spi_transfer(FIFO_STATUS); + rf24_fifo = spi_transfer(0); + rf24_csnHi(); +} + +void rf24_setup() +{ + CE_PIN_DDR |= _BV(CE_PIN_BIT); + CSN_PIN_DDR |= _BV(CSN_PIN_BIT); + CE_PIN_PORT &= ~_BV(CE_PIN_BIT); + CSN_PIN_PORT |= _BV(CSN_PIN_BIT); +} + void rf24_init() { - //CE_PIN_DDR |= _BV(CE_PIN_BIT); - CSN_PIN_DDR |= _BV(CSN_PIN_BIT); - - rf24_ceLow(); - rf24_csnHi(); - - // Initialize spi module - spi_begin(); - _delay_ms(2); - rf24_configure(); - + rf24_write_reg(CONFIG,rf24_CONFIG); + rf24_write_reg(EN_AA,0); + rf24_write_reg(EN_RXADDR,0x3F); + rf24_write_reg(SETUP_AW,0x03); + rf24_write_reg(SETUP_RETR,0x00); + rf24_write_reg(RF_CH,90); + rf24_write_reg(RF_SETUP,(1<> 1; + if(pipe==7) return 0; + int len = plens[pipe]; + + rf24_buffer[0]= R_RX_PAYLOAD; + spi_transfer_rf24(rf24_buffer,rf24_buffer,len+1); + + memcpy ( buffer, rf24_buffer+1,len); + return len; +} + +int rf24_send(uint8_t * buffer, int len){ + if (len> 32 ) return -1; + int cpt=20000; + rf24_update_fifo_status(); + while((cpt--)&&(rf24_fifo & 0x20)){ + _delay_us(1); + rf24_update_fifo_status(); } + if(cpt==0 && (rf24_fifo & 0x20)) return 0; + + memcpy(rf24_buffer+1,buffer,len); + rf24_buffer[0]=W_TX_PAYLOAD; + + spi_transfer_rf24(rf24_buffer,rf24_buffer,plens[0]); + return plens[0]; } -void inline rf24_transmitSync(uint8_t *dataout,uint8_t len){ - uint8_t i; - for(i = 0;i < len;i++){ - spi_transfer(dataout[i]); +int rf24_waitforTX() +{ + int cpt=2000; + rf24_update_fifo_status(); + while((cpt--)&&!(rf24_fifo & 0x10)){ + _delay_us(1); + rf24_update_fifo_status(); } + return cpt==0; } - -void inline rf24_configRegister(uint8_t reg, uint8_t value) -// Clocks only one byte into the given MiRF register -{ - rf24_csnLow(); - spi_transfer(W_REGISTER | (REGISTER_MASK & reg)); - spi_transfer(value); - rf24_csnHi(); -} - -void inline rf24_readRegister(uint8_t reg, uint8_t * value, uint8_t len) -// Reads an array of bytes from the given start position in the MiRF registers. -{ - rf24_csnLow(); - spi_transfer(R_REGISTER | (REGISTER_MASK & reg)); - rf24_transferSync(value,value,len); - rf24_csnHi(); -} - - - -void inline rf24_writeRegister(uint8_t reg, uint8_t * value, uint8_t len) -// Writes an array of bytes into inte the MiRF registers. -{ - rf24_csnLow(); - spi_transfer(W_REGISTER | (REGISTER_MASK & reg)); - rf24_transmitSync(value,len); - rf24_csnHi(); -} - -void rf24_getData(uint8_t * data,uint8_t len) -{ - rf24_csnLow(); // Pull down chip select - spi_transfer( R_RX_PAYLOAD ); // Send cmd to read rx payload - rf24_transferSync(data,data,len); // Read payload - rf24_csnHi(); // Pull up chip select - // NVI: per product spec, p 67, note c: - // "The RX_DR IRQ is asserted by a new packet arrival event. The procedure - // for handling this interrupt should be: 1) read payload through SPI, - // 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more - // payloads available in RX FIFO, 4) if there are more data in RX FIFO, - // repeat from step 1)." - // So if we're going to clear RX_DR here, we need to check the RX FIFO - // in the dataReady() function - rf24_configRegister(STATUS,(1<to_read && to_read>0 ) len=to_read; - - rf24_csnLow(); // Pull down chip select - spi_transfer( R_RX_PAYLOAD ); // Send cmd to read rx payload - rf24_transferSync(data,data,len); // Read payload - - if(to_read!=len){ - to_read-=len; - while((to_read--)>0) // read remaining - spi_transfer(0); - } - rf24_csnHi(); // Pull up chip select - // NVI: per product spec, p 67, note c: - // "The RX_DR IRQ is asserted by a new packet arrival event. The procedure - // for handling this interrupt should be: 1) read payload through SPI, - // 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more - // payloads available in RX FIFO, 4) if there are more data in RX FIFO, - // repeat from step 1)." - // So if we're going to clear RX_DR here, we need to check the RX FIFO - // in the dataReady() function - rf24_configRegister(STATUS,(1< +#include + +#ifndef RF24_h +#define RF24_h + #include "nRF24L01.h" -#include "spi.h" -#include -#include "defines.h" +void rf24_write_lreg(const uint8_t reg, const uint8_t * val, size_t len); +void rf24_write_reg(const uint8_t reg, const uint8_t val); +uint8_t rf24_read_reg(const uint8_t reg); +void rf24_update_fifo_status(); -#ifdef __cplusplus -extern "C"{ -#endif - +extern uint8_t rf24_status; +extern uint8_t rf24_fifo; void rf24_init(); -void rf24_configRegister(uint8_t reg, uint8_t value); -void rf24_readRegister(uint8_t reg, uint8_t * value, uint8_t len); -void rf24_writeRegister(uint8_t reg, uint8_t * value, uint8_t len); - -void rf24_getData(uint8_t * data,uint8_t len); -uint8_t rf24_getDataDL(uint8_t * data,uint8_t len); -uint8_t rf24_dataReady(); -uint8_t rf24_rxFifoEmpty(); - - -void rf24_send(uint8_t * value,uint8_t len); -uint8_t rf24_isSending(); -uint8_t rf24_getStatus(); - -void rf24_powerUpRx(); -void rf24_powerUpTx(); -void rf24_powerDown(); -void rf24_flushRx(); -void rf24_configure(); - - -extern uint8_t rf24_CONFIG; -extern uint8_t rf24_EN_AA; -extern uint8_t rf24_EN_RXADDR; -extern uint8_t rf24_SETUP_AW; -extern uint8_t rf24_SETUP_RETR; -extern uint8_t rf24_RF_CH; -extern uint8_t rf24_RF_SETUP; -extern uint8_t rf24_FEATURE; -extern uint8_t rf24_DYNPD; -extern uint8_t rf24_RX_PW[6]; +/* +void rf24_Off(); +void rf24_RXMode(); +void rf24_TXMode(); +int rf24_receive(uint8_t * buffer); +int rf24_send(uint8_t * buffer, int len); +int rf24_waitforTX(); +*/ #if defined (__AVR_ATtiny84__) || defined (__AVR_ATtiny84A__) @@ -63,10 +45,33 @@ extern uint8_t rf24_RX_PW[6]; #define CSN_PIN_DDR DDRC #define CSN_PIN_BIT PC6 +#elif defined(__AVR_ATmega32A__) + +// CARTE PYRORF + +#define CE_PIN_PORT PORTB +#define CE_PIN_DDR DDRB +#define CE_PIN_BIT PB0 + +#define CSN_PIN_PORT PORTB +#define CSN_PIN_DDR DDRB +#define CSN_PIN_BIT PB1 + + +#elif defined(__AVR_ATmega2560__) + +// ARDUINO MEGA + +#define CE_PIN_PORT PORTL +#define CE_PIN_DDR DDRL +#define CE_PIN_BIT PL0 + +#define CSN_PIN_PORT PORTL +#define CSN_PIN_DDR DDRL +#define CSN_PIN_BIT PL1 + + #endif -#ifdef __cplusplus -} // extern "C" #endif -