270 lines
7.4 KiB
C
270 lines
7.4 KiB
C
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#include "rf24.h"
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#include <util/delay.h>
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uint8_t PTX=0;
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uint8_t rf24_CONFIG = _BV(EN_CRC) | _BV(CRCO);
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uint8_t rf24_EN_AA = 0x3F; //ENAA_P0 - ENAA_P5
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uint8_t rf24_EN_RXADDR = _BV(ERX_P0)|_BV(ERX_P1);
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uint8_t rf24_SETUP_AW = 0x03; // 5 bytes addresses
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uint8_t rf24_SETUP_RETR = 0x03;
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uint8_t rf24_RF_CH = 0x02; // Channel
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uint8_t rf24_RF_SETUP = _BV(RF_DR_HIGH) | _BV(RF_PWR_LOW) | _BV(RF_PWR_HIGH);
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uint8_t rf24_FEATURE = 0;
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uint8_t rf24_DYNPD= 0;
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uint8_t rf24_RX_PW[6] = { 32,32,0,0,0,0 };
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void inline rf24_ceHi(){
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//CE_PIN_PORT |= _BV(CE_PIN_BIT);
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}
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void inline rf24_ceLow(){
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//CE_PIN_PORT &= ~_BV(CE_PIN_BIT);
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}
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void inline rf24_csnHi(){
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CSN_PIN_PORT |= _BV(CSN_PIN_BIT);
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}
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void inline rf24_csnLow(){
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CSN_PIN_PORT &= ~_BV(CSN_PIN_BIT);
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}
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void rf24_init()
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{
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//CE_PIN_DDR |= _BV(CE_PIN_BIT);
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CSN_PIN_DDR |= _BV(CSN_PIN_BIT);
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rf24_ceLow();
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rf24_csnHi();
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// Initialize spi module
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spi_begin();
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_delay_ms(2);
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rf24_configure();
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}
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void inline rf24_transferSync(uint8_t *dataout,uint8_t *datain,uint8_t len){
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uint8_t i;
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for(i = 0;i < len;i++){
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datain[i] = spi_transfer(dataout[i]);
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}
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}
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void inline rf24_transmitSync(uint8_t *dataout,uint8_t len){
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uint8_t i;
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for(i = 0;i < len;i++){
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spi_transfer(dataout[i]);
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}
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}
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void inline rf24_configRegister(uint8_t reg, uint8_t value)
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// Clocks only one byte into the given MiRF register
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{
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rf24_csnLow();
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spi_transfer(W_REGISTER | (REGISTER_MASK & reg));
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spi_transfer(value);
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rf24_csnHi();
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}
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void inline rf24_readRegister(uint8_t reg, uint8_t * value, uint8_t len)
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// Reads an array of bytes from the given start position in the MiRF registers.
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{
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rf24_csnLow();
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spi_transfer(R_REGISTER | (REGISTER_MASK & reg));
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rf24_transferSync(value,value,len);
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rf24_csnHi();
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}
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void inline rf24_writeRegister(uint8_t reg, uint8_t * value, uint8_t len)
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// Writes an array of bytes into inte the MiRF registers.
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{
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rf24_csnLow();
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spi_transfer(W_REGISTER | (REGISTER_MASK & reg));
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rf24_transmitSync(value,len);
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rf24_csnHi();
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}
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void rf24_getData(uint8_t * data,uint8_t len)
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{
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rf24_csnLow(); // Pull down chip select
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spi_transfer( R_RX_PAYLOAD ); // Send cmd to read rx payload
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rf24_transferSync(data,data,len); // Read payload
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rf24_csnHi(); // Pull up chip select
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// NVI: per product spec, p 67, note c:
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// "The RX_DR IRQ is asserted by a new packet arrival event. The procedure
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// for handling this interrupt should be: 1) read payload through SPI,
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// 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more
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// payloads available in RX FIFO, 4) if there are more data in RX FIFO,
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// repeat from step 1)."
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// So if we're going to clear RX_DR here, we need to check the RX FIFO
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// in the dataReady() function
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rf24_configRegister(STATUS,(1<<RX_DR)); // Reset status register
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}
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uint8_t rf24_getDataDL(uint8_t * data,uint8_t len)
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// Reads payload bytes into data array
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{
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uint8_t to_read;
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rf24_csnLow(); // Pull down chip select
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spi_transfer( R_RX_PL_WID ); // Send cmd to read rx payload len
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to_read = spi_transfer(0); // Read payload
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rf24_csnHi(); // Pull up chip select
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if(len>to_read && to_read>0 ) len=to_read;
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rf24_csnLow(); // Pull down chip select
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spi_transfer( R_RX_PAYLOAD ); // Send cmd to read rx payload
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rf24_transferSync(data,data,len); // Read payload
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if(to_read!=len){
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to_read-=len;
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while((to_read--)>0) // read remaining
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spi_transfer(0);
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}
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rf24_csnHi(); // Pull up chip select
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// NVI: per product spec, p 67, note c:
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// "The RX_DR IRQ is asserted by a new packet arrival event. The procedure
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// for handling this interrupt should be: 1) read payload through SPI,
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// 2) clear RX_DR IRQ, 3) read FIFO_STATUS to check if there are more
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// payloads available in RX FIFO, 4) if there are more data in RX FIFO,
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// repeat from step 1)."
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// So if we're going to clear RX_DR here, we need to check the RX FIFO
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// in the dataReady() function
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rf24_configRegister(STATUS,(1<<RX_DR)); // Reset status register
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return to_read;
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}
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uint8_t inline rf24_dataReady()
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// Checks if data is available for reading
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{
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// See note in getData() function - just checking RX_DR isn't good enough
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uint8_t status = rf24_getStatus();
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// We can short circuit on RX_DR, but if it's not set, we still need
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// to check the FIFO for any pending packets
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if ( status & (1 << RX_DR) ) return 1;
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return !rf24_rxFifoEmpty();
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}
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uint8_t inline rf24_rxFifoEmpty(){
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uint8_t fifoStatus;
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rf24_readRegister(FIFO_STATUS,&fifoStatus,sizeof(fifoStatus));
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return (fifoStatus & (1 << RX_EMPTY));
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}
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void rf24_send(uint8_t * value,uint8_t len)
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// Sends a data package to the default address. Be sure to send the correct
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// amount of bytes as configured as payload on the receiver.
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{
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uint8_t status;
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status = rf24_getStatus();
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if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
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rf24_configRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
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}
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rf24_ceLow();
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rf24_powerUpTx(); // Set to transmitter mode , Power up
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rf24_csnLow(); // Pull down chip select
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spi_transfer( FLUSH_TX ); // Write cmd to flush tx fifo
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rf24_csnHi(); // Pull up chip select
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rf24_csnLow(); // Pull down chip select
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spi_transfer( W_TX_PAYLOAD ); // Write cmd to write payload
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rf24_transmitSync(value,len); // Write payload
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rf24_csnHi(); // Pull up chip select
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rf24_ceHi(); // Start transmission
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}
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uint8_t inline rf24_isSending(){
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uint8_t status;
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if(PTX){
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status = rf24_getStatus();
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/*
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* if sending successful (TX_DS) or max retries exceded (MAX_RT).
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*/
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if((status & ((1 << TX_DS) | (1 << MAX_RT)))){
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return 0;
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}
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return 1;
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}
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return 0;
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}
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uint8_t inline rf24_getStatus(){
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uint8_t rv;
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rf24_csnLow();
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rv=spi_transfer(NOP);
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rf24_csnHi();
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return rv;
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}
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void inline rf24_powerUpRx(){
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PTX = 0;
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rf24_ceLow();
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rf24_configRegister(CONFIG, rf24_CONFIG | ( (1<<PWR_UP) | (1<<PRIM_RX) ) );
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rf24_ceHi();
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rf24_configRegister(STATUS,(1 << TX_DS) | (1 << MAX_RT));
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}
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void inline rf24_flushRx(){
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rf24_csnLow();
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spi_transfer( FLUSH_RX );
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rf24_csnHi();
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}
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void inline rf24_powerUpTx(){
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PTX = 1;
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rf24_configRegister(CONFIG, rf24_CONFIG | ( (1<<PWR_UP) | (0<<PRIM_RX) ) );
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}
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void inline rf24_powerDown(){
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rf24_ceLow();
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rf24_configRegister(CONFIG, rf24_CONFIG );
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}
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void rf24_configure(){
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uint8_t data;
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rf24_configRegister(CONFIG,rf24_CONFIG);
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rf24_configRegister(FEATURE,rf24_FEATURE);
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// Check Feature register ...
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rf24_readRegister(FEATURE,&data,1);
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if(rf24_FEATURE != data){ // ACTIVATE & retry
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rf24_csnLow();
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spi_transfer(ACTIVATE);
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spi_transfer(0x73);
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rf24_csnHi();
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rf24_configRegister(FEATURE,rf24_FEATURE);
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}
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rf24_configRegister(EN_AA,rf24_EN_AA);
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rf24_configRegister(EN_RXADDR,rf24_EN_RXADDR);
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rf24_configRegister(SETUP_AW,rf24_SETUP_AW);
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rf24_configRegister(SETUP_RETR,rf24_SETUP_RETR);
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rf24_configRegister(RF_CH,rf24_RF_CH);
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rf24_configRegister(RF_SETUP,rf24_RF_SETUP);
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rf24_configRegister(DYNPD,rf24_DYNPD);
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for(int i=0; i<6;i++)
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rf24_configRegister(RX_PW_P0+i,rf24_RX_PW[i]);
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}
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