#include "rf24.h"
#include "spi.h"
#include <unistd.h>
#include <string.h>
#include <util/delay.h>

#include "lcd.h"

uint8_t rf24_buffer[33];

uint8_t plens[]={32,12,12,12,12,12};
uint8_t lenregs[]={RX_PW_P0,RX_PW_P1,RX_PW_P2,RX_PW_P3,RX_PW_P4,RX_PW_P5};
uint8_t rf24_CONFIG = _BV(MASK_TX_DS)|_BV(MASK_MAX_RT);
uint8_t rf24_status;
uint8_t rf24_fifo;

uint8_t rf24_addr_sl[]={ 0xE7, 0xE7, 0xE7, 0xE7, 0xE7 };
uint8_t rf24_addr_mstr[]={ 0xC2, 0xC2, 0xC2, 0xC2, 0xC1 };


void inline rf24_ceHi(){
    CE_PIN_PORT |= _BV(CE_PIN_BIT);
}

void inline rf24_ceLow(){
    CE_PIN_PORT &= ~_BV(CE_PIN_BIT);
}

void inline rf24_csnHi(){
    CSN_PIN_PORT |= _BV(CSN_PIN_BIT);
}

void inline rf24_csnLow(){
    CSN_PIN_PORT &= ~_BV(CSN_PIN_BIT);
}


void rf24_spi_transfer(uint8_t const *tx, uint8_t *rx, size_t len){
	rf24_csnLow();
		while(len--) *(rx++)=spi_transfer(*(tx++));
	rf24_csnHi();
}

void rf24_write_lreg(const uint8_t reg, const uint8_t * val, size_t len)
{
	rf24_csnLow();
		spi_transfer(W_REGISTER | reg);
		while(len--) spi_transfer(*(val++));
	rf24_csnHi();
}

void rf24_write_reg(const uint8_t reg, const uint8_t val)
{
	rf24_csnLow();
		spi_transfer(W_REGISTER | reg);
		spi_transfer(val);
	rf24_csnHi();
}

uint8_t rf24_read_reg(const uint8_t reg)
{
	rf24_csnLow();
		spi_transfer(R_REGISTER | reg);
		uint8_t ret = spi_transfer(0);
	rf24_csnHi();
    return ret;
}


void rf24_update_status()
{
	rf24_csnLow();
		rf24_status = spi_transfer(NOP);
	rf24_csnHi();
}

void rf24_update_fifo_status()
{
	rf24_csnLow();
		rf24_status = spi_transfer(FIFO_STATUS);
		rf24_fifo = spi_transfer(0);
	rf24_csnHi();
}

void rf24_setup()
{
	CE_PIN_DDR |= _BV(CE_PIN_BIT);
	CSN_PIN_DDR |= _BV(CSN_PIN_BIT);
	rf24_ceLow();
	rf24_csnHi();
	
}

void rf24_init()
{
	rf24_write_reg(CONFIG,rf24_CONFIG);
	rf24_write_reg(EN_AA,0);
	rf24_write_reg(EN_RXADDR,_BV(ERX_P0));
	rf24_write_reg(SETUP_AW,0x03);
	rf24_write_reg(SETUP_RETR,0x00);
	rf24_write_reg(RF_CH,90);
	rf24_write_reg(RF_SETUP,_BV(RF_DR_LOW)|_BV(RF_PWR_HIGH)|_BV(RF_PWR_LOW));
	rf24_write_lreg(RX_ADDR_P0,rf24_addr_sl,5);
	rf24_write_lreg(TX_ADDR,rf24_addr_mstr,5);
	rf24_write_reg(RX_PW_P0,plens[0]);
	rf24_write_reg(DYNPD,0);
	rf24_write_reg(FEATURE,0);
	
	rf24_Off();
	
}


void rf24_Off()
{
	rf24_write_reg(CONFIG,rf24_CONFIG&0xF8);
	rf24_csnLow();
	spi_transfer(FLUSH_RX);
	rf24_csnHi();	
	rf24_csnLow();
	spi_transfer(FLUSH_TX);
	rf24_csnHi();	
	rf24_write_reg(STATUS,0xFF);
}

void rf24_RXMode()
{
	rf24_ceLow();
	rf24_csnLow();
	spi_transfer(FLUSH_RX);
	rf24_csnHi();	
	rf24_write_reg(CONFIG,rf24_CONFIG|0x03);
	rf24_ceHi();
}

int rf24_receive(uint8_t * buffer)
{
	rf24_update_status();
	int pipe = (rf24_status & 0x0E) >> 1;
	if(pipe==7) return 0;
	int len = plens[pipe];
	int i=len;
	rf24_csnLow();
	spi_transfer(R_RX_PAYLOAD);
	while (i--)
		*(buffer++) = spi_transfer(NOP);
	rf24_csnHi();
	
	rf24_write_reg(STATUS,_BV(RX_DR));
	return len;
}


/*

void rf24_TXMode()
{
	rf24_Off();
	_delay_us(1000);
	rf24_buffer[0]=FLUSH_TX;
	spi_transfer_rf24(rf24_buffer,rf24_buffer,1);
	rf24_write_reg(CONFIG,rf24_CONFIG|0x02);
	_delay_us(1000);
}

int rf24_receive(uint8_t * buffer)
{
	rf24_update_fifo_status();
	if(rf24_fifo&1) return 0;
	int pipe = (rf24_status & 0x0E) >> 1;
	if(pipe==7) return 0;
	int len = plens[pipe];

	rf24_buffer[0]= R_RX_PAYLOAD;
	spi_transfer_rf24(rf24_buffer,rf24_buffer,len+1);

	memcpy ( buffer, rf24_buffer+1,len);
	return len;
}

int rf24_send(uint8_t * buffer, int len){
	if (len> 32 ) return -1;
	int cpt=20000;
	rf24_update_fifo_status();
	while((cpt--)&&(rf24_fifo & 0x20)){
		_delay_us(1);
		rf24_update_fifo_status();
	}
	if(cpt==0 && (rf24_fifo & 0x20)) return 0;
	
	memcpy(rf24_buffer+1,buffer,len);
	rf24_buffer[0]=W_TX_PAYLOAD;
	
	spi_transfer_rf24(rf24_buffer,rf24_buffer,plens[0]);
	return plens[0];
}

int rf24_waitforTX()
{
	int cpt=2000;
	rf24_update_fifo_status();
	while((cpt--)&&!(rf24_fifo & 0x10)){
		_delay_us(1);
		rf24_update_fifo_status();
	}
	return cpt==0;
}
*/