diff --git a/rf24.c b/rf24.c
index e97fa8a..c1291ce 100644
--- a/rf24.c
+++ b/rf24.c
@@ -7,9 +7,9 @@
 
 uint8_t rf24_buffer[33];
 
-uint8_t plens[]={24,12,12,12,12,12};
+uint8_t plens[]={32,12,12,12,12,12};
 uint8_t lenregs[]={RX_PW_P0,RX_PW_P1,RX_PW_P2,RX_PW_P3,RX_PW_P4,RX_PW_P5};
-uint8_t rf24_CONFIG = 0;
+uint8_t rf24_CONFIG = _BV(MASK_TX_DS)|_BV(MASK_MAX_RT);
 uint8_t rf24_status;
 uint8_t rf24_fifo;
 
@@ -85,26 +85,14 @@ void rf24_init()
 {
 	rf24_write_reg(CONFIG,rf24_CONFIG);
 	rf24_write_reg(EN_AA,0);
-	rf24_write_reg(EN_RXADDR,0x3F);
+	rf24_write_reg(EN_RXADDR,_BV(ERX_P0));
 	rf24_write_reg(SETUP_AW,0x03);
 	rf24_write_reg(SETUP_RETR,0x00);
 	rf24_write_reg(RF_CH,90);
-	rf24_write_reg(RF_SETUP,(1<<RF_DR_LOW)|(1<<RF_PWR_HIGH)|(1<<RF_PWR_LOW));
-	rf24_write_reg(OBSERVE_TX,0);
-	rf24_write_reg(RPD,0);
-	rf24_write_lreg(RX_ADDR_P0,rf24_addr_P0,5);
-	rf24_write_lreg(RX_ADDR_P1,rf24_addr_P1,5);
-	rf24_write_reg(RX_ADDR_P2,0xC2);
-	rf24_write_reg(RX_ADDR_P2,0xC3);
-	rf24_write_reg(RX_ADDR_P2,0xC4);
-	rf24_write_reg(RX_ADDR_P2,0xC5);
-	rf24_write_lreg(TX_ADDR,rf24_addr_P0,5);
+	rf24_write_reg(RF_SETUP,_BV(RF_DR_LOW)|_BV(RF_PWR_HIGH)|_BV(RF_PWR_LOW));
+	rf24_write_lreg(RX_ADDR_P0,rf24_addr_sl,5);
+	rf24_write_lreg(TX_ADDR,rf24_addr_mstr,5);
 	rf24_write_reg(RX_PW_P0,plens[0]);
-	rf24_write_reg(RX_PW_P1,plens[1]);
-	rf24_write_reg(RX_PW_P2,plens[2]);
-	rf24_write_reg(RX_PW_P3,plens[3]);
-	rf24_write_reg(RX_PW_P4,plens[4]);
-	rf24_write_reg(RX_PW_P5,plens[5]);
 	rf24_write_reg(DYNPD,0);
 	rf24_write_reg(FEATURE,0);