commit 5e37ce1f6d2051873c7708948b8f8a8e6bc57bf0 Author: Arnaud Houdelette Date: Mon Feb 8 16:06:21 2016 +0100 initial commit diff --git a/domopi-cache.lib b/domopi-cache.lib new file mode 100644 index 0000000..cfa4a9c --- /dev/null +++ b/domopi-cache.lib @@ -0,0 +1,334 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# +3V3 +# +DEF +3V3 #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "+3V3" 0 140 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS +3.3V +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +3V3 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# +5V +# +DEF +5V #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -150 50 H I C CNN +F1 "+5V" 0 140 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 1 0 -30 50 0 100 N +P 2 0 1 0 0 0 0 100 N +P 2 0 1 0 0 100 30 50 N +X +5V 1 0 0 0 U 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# ATTINY24A-P +# +DEF ATTINY24A-P IC 0 40 Y Y 1 F N +F0 "IC" -850 750 40 H V C CNN +F1 "ATTINY24A-P" 700 -750 40 H V C CNN +F2 "DIP14" 0 -200 35 H V C CIN +F3 "" 0 0 60 H V C CNN +ALIAS ATTINY44A-P ATTINY84A-P +DRAW +S 900 700 -900 -700 0 1 10 f +X VCC 1 -1050 600 150 R 40 40 1 1 W +X (PCINT8/CLKI/XTAL1)PB0 2 1050 -300 150 L 40 40 1 1 B +X (PCINT9/XTAL2)PB1 3 1050 -400 150 L 40 40 1 1 B +X (PCINT11/dW/~RESET~)PB3 4 1050 -600 150 L 40 40 1 1 B +X (PCINT10/CKOUT/OC0A/INT0)PB2 5 1050 -500 150 L 40 40 1 1 B +X (PCINT7/ICP/OC0B/ADC7)PA7 6 1050 -100 150 L 40 40 1 1 B +X (PCINT6/SDA/DI/MOSI/OC1A/ADC6)PA6 7 1050 0 150 L 40 40 1 1 B +X (PCINT5/DO/MISO/OC1B/ADC5)PA5 8 1050 100 150 L 40 40 1 1 B +X (PCINT4/USCK/SCL/T1/ADC4)PA4 9 1050 200 150 L 40 40 1 1 B +X (PCINT3/T0/ADC3)PA3 10 1050 300 150 L 40 40 1 1 B +X (PCINT2/AIN1/ADC2)PA2 11 1050 400 150 L 40 40 1 1 B +X (PCINT1/AIN0/ADC1)PA1 12 1050 500 150 L 40 40 1 1 B +X (PCINT0/AREF/ADC0)PA0 13 1050 600 150 L 40 40 1 1 B +X GND 14 -1050 -600 150 R 40 40 1 1 W +ENDDRAW +ENDDEF +# +# CONN_01X01 +# +DEF CONN_01X01 P 0 40 Y N 1 F N +F0 "P" 0 100 50 H V C CNN +F1 "CONN_01X01" 100 0 50 V V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + Pin_Header_Straight_1X01 + Pin_Header_Angled_1X01 + Socket_Strip_Straight_1X01 + Socket_Strip_Angled_1X01 +$ENDFPLIST +DRAW +S -50 5 10 -5 0 1 0 N +S -50 50 50 -50 0 1 0 N +X P1 1 -200 0 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# CONN_01X02 +# +DEF CONN_01X02 P 0 40 Y N 1 F N +F0 "P" 0 150 50 H V C CNN +F1 "CONN_01X02" 100 0 50 V V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + Pin_Header_Straight_1X02 + Pin_Header_Angled_1X02 + Socket_Strip_Straight_1X02 + Socket_Strip_Angled_1X02 +$ENDFPLIST +DRAW +S -50 -45 10 -55 0 1 0 N +S -50 55 10 45 0 1 0 N +S -50 100 50 -100 0 1 0 N +X P1 1 -200 50 150 R 50 50 1 1 P +X P2 2 -200 -50 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# CONN_01X04 +# +DEF CONN_01X04 P 0 40 Y N 1 F N +F0 "P" 0 250 50 H V C CNN +F1 "CONN_01X04" 100 0 50 V V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + Pin_Header_Straight_1X04 + Pin_Header_Angled_1X04 + Socket_Strip_Straight_1X04 + Socket_Strip_Angled_1X04 +$ENDFPLIST +DRAW +S -50 -145 10 -155 0 1 0 N +S -50 -45 10 -55 0 1 0 N +S -50 55 10 45 0 1 0 N +S -50 155 10 145 0 1 0 N +S -50 200 50 -200 0 1 0 N +X P1 1 -200 150 150 R 50 50 1 1 P +X P2 2 -200 50 150 R 50 50 1 1 P +X P3 3 -200 -50 150 R 50 50 1 1 P +X P4 4 -200 -150 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# CONN_02X04 +# +DEF CONN_02X04 P 0 1 Y N 1 F N +F0 "P" 0 250 50 H V C CNN +F1 "CONN_02X04" 0 -250 50 H V C CNN +F2 "" 0 -1200 60 H V C CNN +F3 "" 0 -1200 60 H V C CNN +$FPLIST + Pin_Header_Straight_2X04 + Pin_Header_Angled_2X04 + Socket_Strip_Straight_2X04 + Socket_Strip_Angled_2X04 +$ENDFPLIST +DRAW +S -100 -145 -50 -155 0 1 0 N +S -100 -45 -50 -55 0 1 0 N +S -100 55 -50 45 0 1 0 N +S -100 155 -50 145 0 1 0 N +S -100 200 100 -200 0 1 0 N +S 50 -145 100 -155 0 1 0 N +S 50 -45 100 -55 0 1 0 N +S 50 55 100 45 0 1 0 N +S 50 155 100 145 0 1 0 N +X P1 1 -250 150 150 R 50 50 1 1 P +X P2 2 250 150 150 L 50 50 1 1 P +X P3 3 -250 50 150 R 50 50 1 1 P +X P4 4 250 50 150 L 50 50 1 1 P +X P5 5 -250 -50 150 R 50 50 1 1 P +X P6 6 250 -50 150 L 50 50 1 1 P +X P7 7 -250 -150 150 R 50 50 1 1 P +X P8 8 250 -150 150 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# CONN_02X20 +# +DEF CONN_02X20 P 0 1 Y N 1 F N +F0 "P" 0 1050 50 H V C CNN +F1 "CONN_02X20" 0 0 50 V V C CNN +F2 "" 0 -950 60 H V C CNN +F3 "" 0 -950 60 H V C CNN +$FPLIST + Pin_Header_Straight_2X20 + Pin_Header_Angled_2X20 + Socket_Strip_Straight_2X20 + Socket_Strip_Angled_2X20 +$ENDFPLIST +DRAW +S -100 -945 -50 -955 0 1 0 N +S -100 -845 -50 -855 0 1 0 N +S -100 -745 -50 -755 0 1 0 N +S -100 -645 -50 -655 0 1 0 N +S -100 -545 -50 -555 0 1 0 N +S -100 -445 -50 -455 0 1 0 N +S -100 -345 -50 -355 0 1 0 N +S -100 -245 -50 -255 0 1 0 N +S -100 -145 -50 -155 0 1 0 N +S -100 -45 -50 -55 0 1 0 N +S -100 55 -50 45 0 1 0 N +S -100 155 -50 145 0 1 0 N +S -100 255 -50 245 0 1 0 N +S -100 355 -50 345 0 1 0 N +S -100 455 -50 445 0 1 0 N +S -100 555 -50 545 0 1 0 N +S -100 655 -50 645 0 1 0 N +S -100 755 -50 745 0 1 0 N +S -100 855 -50 845 0 1 0 N +S -100 955 -50 945 0 1 0 N +S -100 1000 100 -1000 0 1 0 N +S 50 -945 100 -955 0 1 0 N +S 50 -845 100 -855 0 1 0 N +S 50 -745 100 -755 0 1 0 N +S 50 -645 100 -655 0 1 0 N +S 50 -545 100 -555 0 1 0 N +S 50 -445 100 -455 0 1 0 N +S 50 -345 100 -355 0 1 0 N +S 50 -245 100 -255 0 1 0 N +S 50 -145 100 -155 0 1 0 N +S 50 -45 100 -55 0 1 0 N +S 50 55 100 45 0 1 0 N +S 50 155 100 145 0 1 0 N +S 50 255 100 245 0 1 0 N +S 50 355 100 345 0 1 0 N +S 50 455 100 445 0 1 0 N +S 50 555 100 545 0 1 0 N +S 50 655 100 645 0 1 0 N +S 50 755 100 745 0 1 0 N +S 50 855 100 845 0 1 0 N +S 50 955 100 945 0 1 0 N +X P1 1 -250 950 150 R 50 50 1 1 P +X P2 2 250 950 150 L 50 50 1 1 P +X P3 3 -250 850 150 R 50 50 1 1 P +X P4 4 250 850 150 L 50 50 1 1 P +X P5 5 -250 750 150 R 50 50 1 1 P +X P6 6 250 750 150 L 50 50 1 1 P +X P7 7 -250 650 150 R 50 50 1 1 P +X P8 8 250 650 150 L 50 50 1 1 P +X P9 9 -250 550 150 R 50 50 1 1 P +X P10 10 250 550 150 L 50 50 1 1 P +X P20 20 250 50 150 L 50 50 1 1 P +X P30 30 250 -450 150 L 50 50 1 1 P +X P40 40 250 -950 150 L 50 50 1 1 P +X P11 11 -250 450 150 R 50 50 1 1 P +X P21 21 -250 -50 150 R 50 50 1 1 P +X P31 31 -250 -550 150 R 50 50 1 1 P +X P12 12 250 450 150 L 50 50 1 1 P +X P22 22 250 -50 150 L 50 50 1 1 P +X P32 32 250 -550 150 L 50 50 1 1 P +X P13 13 -250 350 150 R 50 50 1 1 P +X P23 23 -250 -150 150 R 50 50 1 1 P +X P33 33 -250 -650 150 R 50 50 1 1 P +X P14 14 250 350 150 L 50 50 1 1 P +X P24 24 250 -150 150 L 50 50 1 1 P +X P34 34 250 -650 150 L 50 50 1 1 P +X P15 15 -250 250 150 R 50 50 1 1 P +X P25 25 -250 -250 150 R 50 50 1 1 P +X P35 35 -250 -750 150 R 50 50 1 1 P +X P16 16 250 250 150 L 50 50 1 1 P +X P26 26 250 -250 150 L 50 50 1 1 P +X P36 36 250 -750 150 L 50 50 1 1 P +X P17 17 -250 150 150 R 50 50 1 1 P +X P27 27 -250 -350 150 R 50 50 1 1 P +X P37 37 -250 -850 150 R 50 50 1 1 P +X P18 18 250 150 150 L 50 50 1 1 P +X P28 28 250 -350 150 L 50 50 1 1 P +X P38 38 250 -850 150 L 50 50 1 1 P +X P19 19 -250 50 150 R 50 50 1 1 P +X P29 29 -250 -450 150 R 50 50 1 1 P +X P39 39 -250 -950 150 R 50 50 1 1 P +ENDDRAW +ENDDEF +# +# CP +# +DEF CP C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "CP" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + CP* + Elko* + TantalC* + C*elec + c_elec* + SMD*_Pol +$ENDFPLIST +DRAW +S -90 20 -90 40 0 1 0 N +S -90 20 90 20 0 1 0 N +S 90 -20 -90 -40 0 1 0 F +S 90 40 -90 40 0 1 0 N +S 90 40 90 20 0 1 0 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 110 -50 70 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# R +# +DEF R R 0 0 N Y 1 F N +F0 "R" 80 0 50 V V C CNN +F1 "R" 0 0 50 V V C CNN +F2 "" -70 0 30 V V C CNN +F3 "" 0 0 30 H V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S -40 -100 40 100 0 1 10 N +X ~ 1 0 150 50 D 60 60 1 1 P +X ~ 2 0 -150 50 U 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/domopi.dsn b/domopi.dsn new file mode 100644 index 0000000..8055737 --- /dev/null +++ b/domopi.dsn @@ -0,0 +1,732 @@ +(pcb /media/smb/arnaud/kicad/domopi/domopi.dsn + (parser + (string_quote ") + (space_in_quoted_tokens on) + (host_cad "KiCad's Pcbnew") + (host_version "(2015-09-30 BZR 6231)-product") + ) + (resolution um 10) + (unit um) + (structure + (layer F.Cu + (type signal) + (property + (index 0) + ) + ) + (layer B.Cu + (type signal) + (property + (index 1) + ) + ) + (boundary + (path pcb 0 66040 -25400 66040 -58420 132080 -58420 132080 -25400 + 66040 -25400 66040 -25400) + ) + (via "Via[0-1]_600:400_um") + (rule + (width 254) + (clearance 254.1) + (clearance 254.1 (type default_smd)) + (clearance 63.5 (type smd_smd)) + ) + ) + (placement + (component Socket_Strips:Socket_Strip_Straight_2x20 + (place P1 68580 -30480 back 180 (PN RASPBERRY)) + ) + (component Pin_Headers:Pin_Header_Straight_1x02 + (place P2 68580 -43180 front 180 (PN CONN_01X02)) + ) + (component Pin_Headers:Pin_Header_Straight_1x01 + (place P5 104140 -55880 front 0 (PN ANT)) + ) + (component "Housings_DIP:DIP-14_W7.62mm" + (place IC1 116840 -50800 front 180 (PN "ATTINY84A-P")) + ) + (component Capacitors_Elko_ThroughHole:Elko_vert_11.2x6.3mm_RM2.5 + (place C1 71120 -50800 front 90 (PN 0.47u)) + (place C3 129540 -30480 front 180 (PN 10u)) + (place C4 86360 -55880 front 90 (PN 10u)) + ) + (component Capacitors_Elko_ThroughHole:Elko_vert_11.5x8mm_RM3.5 + (place C2 86360 -43180 front 270 (PN 33u)) + ) + (component "Power_Integrations:TO-220" + (place U1 78740 -48260 front 90 (PN "LM3940IT-3.3")) + ) + (component Resistors_ThroughHole:Resistor_Vertical_RM5mm + (place R1 83820 -35560 front 90 (PN 1k)) + (place R2 93980 -45720 front 90 (PN 1k)) + (place R3 93980 -35560 front 90 (PN 1k)) + (place R4 99060 -35560 front 90 (PN 1k)) + (place R5 73660 -35560 front 90 (PN 1k)) + (place R6 88900 -35560 front 90 (PN 1k)) + (place R7 99060 -45720 front 90 (PN 1k)) + (place R8 104140 -35560 front 90 (PN 1k)) + (place R9 78740 -35560 front 90 (PN 1k)) + (place R10 104140 -45720 front 90 (PN 4.7k)) + ) + (component Socket_Strips:Socket_Strip_Straight_1x04 + (place P4 91440 -55880 front 0 (PN RFTX)) + (place P7 121920 -55880 front 0 (PN RFRX)) + ) + (component Socket_Strips:Socket_Strip_Straight_1x03 + (place P6 124460 -50800 front 0 (PN CONN_01X03)) + ) + (component Pin_Headers:Pin_Header_Straight_2x04 + (place P3 127000 -38100 front 0 (PN nRF24L01P)) + ) + ) + (library + (image Socket_Strips:Socket_Strip_Straight_2x20 + (outline (path signal 50 -1750 1750 -1750 -4300)) + (outline (path signal 50 50050 1750 50050 -4300)) + (outline (path signal 50 -1750 1750 50050 1750)) + (outline (path signal 50 -1750 -4300 50050 -4300)) + (outline (path signal 150 49530 -3810 -1270 -3810)) + (outline (path signal 150 1270 1270 49530 1270)) + (outline (path signal 150 49530 -3810 49530 1270)) + (outline (path signal 150 -1270 -3810 -1270 -1270)) + (outline (path signal 150 0 1550 -1550 1550)) + (outline (path signal 150 -1270 -1270 1270 -1270)) + (outline (path signal 150 1270 -1270 1270 1270)) + (outline (path signal 150 -1550 1550 -1550 0)) + (pin Rect[A]Pad_1727.2x1727.2_um 1 0 0) + (pin Oval[A]Pad_1727.2x1727.2_um 2 0 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 3 2540 0) + (pin Oval[A]Pad_1727.2x1727.2_um 4 2540 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 5 5080 0) + (pin Oval[A]Pad_1727.2x1727.2_um 6 5080 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 7 7620 0) + (pin Oval[A]Pad_1727.2x1727.2_um 8 7620 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 9 10160 0) + (pin Oval[A]Pad_1727.2x1727.2_um 10 10160 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 11 12700 0) + (pin Oval[A]Pad_1727.2x1727.2_um 12 12700 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 13 15240 0) + (pin Oval[A]Pad_1727.2x1727.2_um 14 15240 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 15 17780 0) + (pin Oval[A]Pad_1727.2x1727.2_um 16 17780 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 17 20320 0) + (pin Oval[A]Pad_1727.2x1727.2_um 18 20320 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 19 22860 0) + (pin Oval[A]Pad_1727.2x1727.2_um 20 22860 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 21 25400 0) + (pin Oval[A]Pad_1727.2x1727.2_um 22 25400 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 23 27940 0) + (pin Oval[A]Pad_1727.2x1727.2_um 24 27940 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 25 30480 0) + (pin Oval[A]Pad_1727.2x1727.2_um 26 30480 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 27 33020 0) + (pin Oval[A]Pad_1727.2x1727.2_um 28 33020 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 29 35560 0) + (pin Oval[A]Pad_1727.2x1727.2_um 30 35560 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 31 38100 0) + (pin Oval[A]Pad_1727.2x1727.2_um 32 38100 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 33 40640 0) + (pin Oval[A]Pad_1727.2x1727.2_um 34 40640 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 35 43180 0) + (pin Oval[A]Pad_1727.2x1727.2_um 36 43180 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 37 45720 0) + (pin Oval[A]Pad_1727.2x1727.2_um 38 45720 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 39 48260 0) + (pin Oval[A]Pad_1727.2x1727.2_um 40 48260 -2540) + ) + (image Pin_Headers:Pin_Header_Straight_1x02 + (outline (path signal 150 1270 -1270 1270 -3810)) + (outline (path signal 150 1550 1550 1550 0)) + (outline (path signal 50 -1750 1750 -1750 -4300)) + (outline (path signal 50 1750 1750 1750 -4300)) + (outline (path signal 50 -1750 1750 1750 1750)) + (outline (path signal 50 -1750 -4300 1750 -4300)) + (outline (path signal 150 1270 -1270 -1270 -1270)) + (outline (path signal 150 -1550 0 -1550 1550)) + (outline (path signal 150 -1550 1550 1550 1550)) + (outline (path signal 150 -1270 -1270 -1270 -3810)) + (outline (path signal 150 -1270 -3810 1270 -3810)) + (pin Rect[A]Pad_2032x2032_um 1 0 0) + (pin Oval[A]Pad_2032x2032_um 2 0 -2540) + ) + (image Pin_Headers:Pin_Header_Straight_1x01 + (outline (path signal 150 1550 1550 1550 0)) + (outline (path signal 50 -1750 1750 -1750 -1750)) + (outline (path signal 50 1750 1750 1750 -1750)) + (outline (path signal 50 -1750 1750 1750 1750)) + (outline (path signal 50 -1750 -1750 1750 -1750)) + (outline (path signal 150 -1550 0 -1550 1550)) + (outline (path signal 150 -1550 1550 1550 1550)) + (outline (path signal 150 -1270 -1270 1270 -1270)) + (pin Rect[A]Pad_2235.2x2235.2_um 1 0 0) + ) + (image "Housings_DIP:DIP-14_W7.62mm" + (outline (path signal 50 -1050 2450 -1050 -17700)) + (outline (path signal 50 8650 2450 8650 -17700)) + (outline (path signal 50 -1050 2450 8650 2450)) + (outline (path signal 50 -1050 -17700 8650 -17700)) + (outline (path signal 150 135 2295 135 1025)) + (outline (path signal 150 7485 2295 7485 1025)) + (outline (path signal 150 7485 -17535 7485 -16265)) + (outline (path signal 150 135 -17535 135 -16265)) + (outline (path signal 150 135 2295 7485 2295)) + (outline (path signal 150 135 -17535 7485 -17535)) + (outline (path signal 150 135 1025 -800 1025)) + (pin Oval[A]Pad_1600x1600_um 1 0 0) + (pin Oval[A]Pad_1600x1600_um 2 0 -2540) + (pin Oval[A]Pad_1600x1600_um 3 0 -5080) + (pin Oval[A]Pad_1600x1600_um 4 0 -7620) + (pin Oval[A]Pad_1600x1600_um 5 0 -10160) + (pin Oval[A]Pad_1600x1600_um 6 0 -12700) + (pin Oval[A]Pad_1600x1600_um 7 0 -15240) + (pin Oval[A]Pad_1600x1600_um 8 7620 -15240) + (pin Oval[A]Pad_1600x1600_um 9 7620 -12700) + (pin Oval[A]Pad_1600x1600_um 10 7620 -10160) + (pin Oval[A]Pad_1600x1600_um 11 7620 -7620) + (pin Oval[A]Pad_1600x1600_um 12 7620 -5080) + (pin Oval[A]Pad_1600x1600_um 13 7620 -2540) + (pin Oval[A]Pad_1600x1600_um 14 7620 0) + ) + (image Capacitors_Elko_ThroughHole:Elko_vert_11.2x6.3mm_RM2.5 + (outline (path signal 150 269.24 2199.64 269.24 1198.88)) + (outline (path signal 150 -231.14 1699.26 769.62 1699.26)) + (outline (path signal 150 269.24 1699.26 769.62 1699.26)) + (outline (path signal 150 269.24 1699.26 269.24 2199.64)) + (outline (path signal 150 -231.14 1699.26 269.24 1699.26)) + (outline (path signal 150 269.24 1699.26 269.24 1300.48)) + (outline (path signal 150 269.24 1300.48 269.24 1198.88)) + (outline (path signal 150 4419.6 0 4265.45 -973.28 3818.08 -1851.29 3121.29 -2548.08 + 2243.28 -2995.45 1270 -3149.6 296.72 -2995.45 -581.288 -2548.08 + -1278.08 -1851.29 -1725.45 -973.28 -1879.6 0 -1725.45 973.28 + -1278.08 1851.29 -581.288 2548.08 296.72 2995.45 1270 3149.6 + 2243.28 2995.45 3121.29 2548.08 3818.08 1851.29 4265.45 973.28)) + (pin Round[A]Pad_1501.14_um 2 2540 0) + (pin Round[A]Pad_1501.14_um 1 0 0) + ) + (image Capacitors_Elko_ThroughHole:Elko_vert_11.5x8mm_RM3.5 + (outline (path signal 150 104.14 2024.38 1130.3 2024.38)) + (outline (path signal 150 629.92 2575.56 629.92 1524)) + (outline (path signal 150 635 2540 635 1524)) + (outline (path signal 150 127 2032 1143 2032)) + (outline (path signal 150 5905.5 0 5709.7 -1236.22 5141.47 -2351.43 4256.44 -3236.47 + 3141.22 -3804.7 1905 -4000.5 668.778 -3804.7 -446.435 -3236.47 + -1331.47 -2351.43 -1899.7 -1236.22 -2095.5 0 -1899.7 1236.22 + -1331.47 2351.43 -446.435 3236.47 668.778 3804.7 1905 4000.5 + 3141.22 3804.7 4256.44 3236.47 5141.47 2351.43 5709.7 1236.22)) + (pin Round[A]Pad_1501.14_um 2 3810 0) + (pin Round[A]Pad_1501.14_um 1 0 0) + ) + (image "Power_Integrations:TO-220" + (outline (path signal 150 4826 1651 4826 -1778)) + (outline (path signal 150 -4826 1651 -4826 -1778)) + (outline (path signal 150 5334 2794 -5334 2794)) + (outline (path signal 150 1778 1778 1778 3048)) + (outline (path signal 150 -1778 1778 -1778 3048)) + (outline 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1270 -1270)) + (outline (path signal 150 1270 -1270 -1270 -1270)) + (outline (path signal 150 -1550 1550 -1550 0)) + (pin Rect[A]Pad_1727.2x1727.2_um 1 0 0) + (pin Oval[A]Pad_1727.2x1727.2_um 2 2540 0) + (pin Oval[A]Pad_1727.2x1727.2_um 3 0 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 4 2540 -2540) + (pin Oval[A]Pad_1727.2x1727.2_um 5 0 -5080) + (pin Oval[A]Pad_1727.2x1727.2_um 6 2540 -5080) + (pin Oval[A]Pad_1727.2x1727.2_um 7 0 -7620) + (pin Oval[A]Pad_1727.2x1727.2_um 8 2540 -7620) + ) + (padstack Round[A]Pad_1501.14_um + (shape (circle F.Cu 1501.14)) + (shape (circle B.Cu 1501.14)) + (attach off) + ) + (padstack Round[A]Pad_1998.98_um + (shape (circle F.Cu 1998.98)) + (shape (circle B.Cu 1998.98)) + (attach off) + ) + (padstack Oval[A]Pad_1600x1600_um + (shape (path F.Cu 1600 0 0 0 0)) + (shape (path B.Cu 1600 0 0 0 0)) + (attach off) + ) + (padstack Oval[A]Pad_1727.2x2032_um + (shape (path F.Cu 1727.2 0 -152.4 0 152.4)) + (shape (path B.Cu 1727.2 0 -152.4 0 152.4)) + (attach off) + ) + (padstack Oval[A]Pad_1727.2x1727.2_um + (shape (path F.Cu 1727.2 0 0 0 0)) + (shape (path B.Cu 1727.2 0 0 0 0)) + (attach off) + ) + (padstack Oval[A]Pad_2032x2540_um + (shape (path F.Cu 2032 0 -254 0 254)) + (shape (path B.Cu 2032 0 -254 0 254)) + (attach off) + ) + (padstack Oval[A]Pad_2032x2032_um + (shape (path F.Cu 2032 0 0 0 0)) + (shape (path B.Cu 2032 0 0 0 0)) + (attach off) + ) + (padstack Rect[A]Pad_2032x2032_um + (shape (rect F.Cu -1016 -1016 1016 1016)) + (shape (rect B.Cu -1016 -1016 1016 1016)) + (attach off) + ) + (padstack Rect[A]Pad_2235.2x2235.2_um + (shape (rect F.Cu -1117.6 -1117.6 1117.6 1117.6)) + (shape (rect B.Cu -1117.6 -1117.6 1117.6 1117.6)) + (attach off) + ) + (padstack Rect[A]Pad_1727.2x2032_um + (shape (rect F.Cu -863.6 -1016 863.6 1016)) + (shape (rect B.Cu -863.6 -1016 863.6 1016)) + (attach off) + ) + (padstack Rect[A]Pad_1727.2x1727.2_um + (shape (rect F.Cu -863.6 -863.6 863.6 863.6)) + (shape (rect B.Cu -863.6 -863.6 863.6 863.6)) + (attach off) + ) + (padstack "Via[0-1]_600:400_um" + (shape (circle F.Cu 600)) + (shape (circle B.Cu 600)) + (attach off) + ) + ) + (network + (net GND + (pins P1-6 P1-20 P2-2 IC1-14 C1-2 C2-2 C3-1 C4-2 U1-2 P4-2 P7-4 P3-2) + ) + (net +3V3 + (pins IC1-1 C2-1 C3-2 U1-3 R10-1 P3-1) + ) + (net +5V + (pins P1-2 P1-4 P2-1 C1-1 C4-1 U1-1 P4-1 P7-1) + ) + (net "Net-(P1-Pad3)" + (pins P1-3) + ) + (net "Net-(P1-Pad5)" + (pins P1-5) + ) + (net "Net-(P1-Pad7)" + (pins P1-7) + ) + (net "Net-(P1-Pad8)" + (pins P1-8 R5-2) + ) + (net "Net-(P1-Pad9)" + (pins P1-9) + ) + (net "Net-(P1-Pad10)" + (pins P1-10 R9-2) + ) + (net "Net-(P1-Pad11)" + (pins P1-11) + ) + (net "Net-(P1-Pad12)" + (pins P1-12) + ) + (net "Net-(P1-Pad13)" + (pins P1-13) + ) + (net "Net-(P1-Pad14)" + (pins P1-14) + ) + (net "Net-(P1-Pad15)" + (pins P1-15 R1-2) + ) + (net "Net-(P1-Pad16)" + (pins P1-16) + ) + (net "Net-(P1-Pad17)" + (pins P1-17) + ) + (net "Net-(P1-Pad18)" + (pins P1-18 R6-2) + ) + (net "Net-(P1-Pad19)" + (pins P1-19 R2-2) + ) + (net "Net-(P1-Pad21)" + (pins P1-21 R3-2) + ) + (net "Net-(P1-Pad22)" + (pins P1-22 R7-2) + ) + (net "Net-(P1-Pad23)" + (pins P1-23 R4-2) + ) + (net "Net-(P1-Pad24)" + (pins P1-24 R8-2) + ) + (net "Net-(P1-Pad25)" + (pins P1-25) + ) + (net "Net-(P1-Pad26)" + (pins P1-26) + ) + (net "Net-(P1-Pad27)" + (pins P1-27) + ) + (net "Net-(P1-Pad28)" + (pins P1-28) + ) + (net "Net-(P1-Pad29)" + (pins P1-29) + ) + (net "Net-(P1-Pad30)" + (pins P1-30) + ) + (net "Net-(P1-Pad31)" + (pins P1-31) + ) + (net "Net-(P1-Pad32)" + (pins P1-32) + ) + (net "Net-(P1-Pad33)" + (pins P1-33) + ) + (net "Net-(P1-Pad34)" + (pins P1-34) + ) + (net "Net-(P1-Pad35)" + (pins P1-35) + ) + (net "Net-(P1-Pad36)" + (pins P1-36) + ) + (net "Net-(P1-Pad37)" + (pins P1-37) + ) + (net "Net-(P1-Pad38)" + (pins P1-38) + ) + (net "Net-(P1-Pad39)" + (pins P1-39) + ) + (net "Net-(P1-Pad40)" + (pins P1-40) + ) + (net CE + (pins R6-1 P3-3) + ) + (net SS0 + (pins R7-1 P3-4) + ) + (net SCK + (pins IC1-9 R4-1 P3-5) + ) + (net MOSI + (pins IC1-7 R2-1 P3-6) + ) + (net MISO + (pins IC1-8 R3-1 P3-7) + ) + (net "/NRF-INT" + (pins P3-8) + ) + (net "/RF433-OUT" + (pins IC1-13 P4-3) + ) + (net "Net-(P4-Pad4)" + (pins P5-1 P4-4) + ) + (net "Net-(IC1-Pad12)" + (pins IC1-12 P6-1) + ) + (net "Net-(IC1-Pad11)" + (pins IC1-11 P6-2) + ) + (net "Net-(IC1-Pad10)" + (pins IC1-10 P6-3) + ) + (net "Net-(P7-Pad2)" + (pins P7-2) + ) + (net "/RF433-IN" + (pins IC1-6 P7-3) + ) + (net "Tiny-RESET" + (pins IC1-4 R1-1 R10-2) + ) + (net TX + (pins IC1-3 R5-1) + ) + (net SS1 + (pins IC1-5 R8-1) + ) + (net RX + (pins IC1-2 R9-1) + ) + (net "Net-(P1-Pad1)" + (pins P1-1) + ) + (class kicad_default "" "/NRF-INT" "/RF433-IN" "/RF433-OUT" CE MISO MOSI + "Net-(IC1-Pad10)" "Net-(IC1-Pad11)" "Net-(IC1-Pad12)" "Net-(P1-Pad1)" + "Net-(P1-Pad10)" "Net-(P1-Pad11)" "Net-(P1-Pad12)" "Net-(P1-Pad13)" + "Net-(P1-Pad14)" "Net-(P1-Pad15)" "Net-(P1-Pad16)" "Net-(P1-Pad17)" + "Net-(P1-Pad18)" "Net-(P1-Pad19)" "Net-(P1-Pad21)" "Net-(P1-Pad22)" + "Net-(P1-Pad23)" "Net-(P1-Pad24)" "Net-(P1-Pad25)" "Net-(P1-Pad26)" + "Net-(P1-Pad27)" "Net-(P1-Pad28)" "Net-(P1-Pad29)" "Net-(P1-Pad3)" "Net-(P1-Pad30)" + "Net-(P1-Pad31)" "Net-(P1-Pad32)" "Net-(P1-Pad33)" "Net-(P1-Pad34)" + "Net-(P1-Pad35)" "Net-(P1-Pad36)" "Net-(P1-Pad37)" "Net-(P1-Pad38)" + "Net-(P1-Pad39)" "Net-(P1-Pad40)" "Net-(P1-Pad5)" "Net-(P1-Pad7)" "Net-(P1-Pad8)" + "Net-(P1-Pad9)" "Net-(P4-Pad4)" "Net-(P7-Pad2)" RX SCK SS0 SS1 TX "Tiny-RESET" + (circuit + (use_via Via[0-1]_600:400_um) + ) + (rule + (width 254) + (clearance 254.1) + ) + ) + (class Power +3V3 +5V GND + (circuit + (use_via Via[0-1]_600:400_um) + ) + (rule + (width 406.4) + (clearance 304.9) + ) + ) + ) + (wiring + (wire (path B.Cu 406.4 129540 -38100 129540 -30480)(net GND)(type protect)) + (wire (path B.Cu 406.4 129092 -53340 127152 -53340)(net GND)(type protect)) + (wire (path B.Cu 406.4 129540 -38100 130912 -39471.6 130912 -51520.5 129092 -53340)(net GND)(type protect)) + (wire (path B.Cu 406.4 127152 -53340 106680 -53340)(net GND)(type protect)) + (wire (path B.Cu 406.4 129540 -55880 129540 -55727.6 127152 -53340)(net GND)(type protect)) + (wire (path B.Cu 406.4 86360 -53340 94074 -53340 106680 -53340)(net GND)(type protect)) + (wire (path B.Cu 406.4 93980 -55880 93980 -53434 94074 -53340)(net GND)(type protect)) + (wire (path B.Cu 406.4 106680 -53340 109220 -50800)(net GND)(type protect)) + (wire (path B.Cu 406.4 86360 -53340 86360 -49530 85090 -48260)(net GND)(type protect)) + (wire (path B.Cu 406.4 78740 -48260 85090 -48260 86360 -46990)(net GND)(type protect)) + (wire (path B.Cu 406.4 71120 -48260 78740 -48260)(net GND)(type protect)) + (wire (path B.Cu 406.4 68580 -40640 69596 -41656 70002.4 -41656 71120 -42773.6 + 71120 -47198.5 71120 -48260)(net GND)(type protect)) + (wire (path B.Cu 406.4 73660 -27940 72288.4 -26568.4 67921.6 -26568.4)(net GND)(type protect)) + (wire (path B.Cu 406.4 67564 -39624 68580 -40640)(net GND)(type protect)) + (wire (path B.Cu 406.4 67921.6 -26568.4 67208.4 -27281.6 67208.4 -39268.4 67564 -39624)(net GND)(type protect)) + (wire (path B.Cu 406.4 73660 -27940 75031.6 -26568.4 90068.4 -26568.4 90576.4 -27076.4 + 91440 -27940)(net GND)(type protect)) + (wire (path F.Cu 406.4 127000 -36830 127000 -38100)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 127102 -36728.4 127000 -36830)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 130198 -36728.4 127102 -36728.4)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 121540 -49276 128014 -49276)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 130912 -46378.4 130912 -37441.6 130198 -36728.4)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 116840 -50800 120016 -50800 121540 -49276)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 128014 -49276 130912 -46378.4)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 127000 -30480 127000 -38100)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 104140 -48219.4 108029 -52108 115532 -52108 116040 -51600 + 116840 -50800)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 87905.6 -45995.6 91636.9 -49726.9 102633 -49726.9 103141 -49218.8 + 104140 -48219.4)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 86360 -43180 87905.6 -44725.6 87905.6 -45995.6)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 78740 -45720 83820 -45720 86360 -43180)(net +3V3)(type protect)) + (wire (path F.Cu 406.4 91440 -55880 91440 -56032.4 92913.2 -57505.6 119024 -57505.6)(net +5V)(type protect)) + (wire (path F.Cu 406.4 120650 -55880 121920 -55880)(net +5V)(type protect)) + (wire (path F.Cu 406.4 119024 -57505.6 120650 -55880)(net +5V)(type protect)) + (wire (path F.Cu 406.4 86360 -55880 91440 -55880)(net +5V)(type protect)) + (wire (path F.Cu 406.4 78740 -50800 81280 -50800 86360 -55880)(net +5V)(type protect)) + (wire (path F.Cu 406.4 71120 -50800 78740 -50800)(net +5V)(type protect)) + (wire (path F.Cu 406.4 68580 -43180 68580 -48260 71120 -50800)(net +5V)(type protect)) + (wire (path F.Cu 406.4 68580 -27940 67056 -29464 67056 -43078.4 67157.6 -43180 + 68580 -43180)(net +5V)(type protect)) + (wire (path F.Cu 406.4 71120 -27940 68580 -27940)(net +5V)(type protect)) + (wire (path B.Cu 254 76200 -27940 74955.4 -29184.6 74955.4 -31762.7 74659.5 -32058.6 + 73660 -33058.1)(net "Net-(P1-Pad8)")(type protect)) + (wire (path B.Cu 254 78740 -27940 77495.4 -29184.6 77495.4 -31813.5 77740.5 -32058.6 + 78740 -33058.1)(net "Net-(P1-Pad10)")(type protect)) + (wire (path B.Cu 254 86360 -30480 83820 -33020 83820 -33058.1)(net "Net-(P1-Pad15)")(type protect)) + (wire (path B.Cu 254 88900 -27940 87655.4 -29184.6 87655.4 -31813.5 87900.5 -32058.6 + 88900 -33058.1)(net "Net-(P1-Pad18)")(type protect)) + (wire (path B.Cu 254 93980 -43218.1 91440 -40678.1 91440 -30480)(net "Net-(P1-Pad19)")(type protect)) + (wire (path B.Cu 254 93980 -33058.1 93980 -30480)(net "Net-(P1-Pad21)")(type protect)) + (wire (path B.Cu 254 99060 -43218.1 97679.5 -41837.6 97679.5 -33481.5)(net "Net-(P1-Pad22)")(type protect)) + (wire (path B.Cu 254 94843.6 -28803.6 93980 -27940)(net "Net-(P1-Pad22)")(type protect)) + (wire (path B.Cu 254 97679.5 -33481.5 95224.6 -31026.6 95224.6 -29184.6 94843.6 -28803.6)(net "Net-(P1-Pad22)")(type protect)) + (wire (path B.Cu 254 99060 -33058.1 96520 -30518.1 96520 -30480)(net "Net-(P1-Pad23)")(type protect)) + (wire (path B.Cu 254 104140 -33058.1 102336 -33058.1 100305 -31026.6 100305 -29882.6 + 99606.6 -29184.6 97764.6 -29184.6 97383.6 -28803.6 96520 -27940)(net "Net-(P1-Pad24)")(type protect)) + (wire (path B.Cu 254 91440 -41910 88900 -39370 88900 -38059.4)(net CE)(type protect)) + (wire (path F.Cu 254 110490 -41910 110418 -41837.6 91512.4 -41837.6 91440 -41910)(net CE)(type protect)) + (wire (path F.Cu 254 110579 -41821 110490 -41910)(net CE)(type protect)) + (wire (path F.Cu 254 120650 -40640 119469 -41821 110579 -41821)(net CE)(type protect)) + (wire (path B.Cu 254 127000 -40640 120650 -40640)(net CE)(type protect)) + (wire (path F.Cu 254 99060 -48219.4 102022 -48219.4 103453 -46788.1 104827 -46788.1 + 105029 -46990)(net SS0)(type protect)) + (wire (path F.Cu 254 120977 -48941 123190 -46727.9)(net SS0)(type protect)) + (wire (path F.Cu 254 105029 -46990 118021 -46990)(net SS0)(type protect)) + (wire (path F.Cu 254 123190 -46727.9 123190 -39370)(net SS0)(type protect)) + (wire (path F.Cu 254 118021 -46990 118021 -46901 120061 -48941 120977 -48941)(net SS0)(type protect)) + (wire (path B.Cu 254 128209 -39395.4 126403 -39395.4 127597 -39395.4)(net SS0)(type protect)) + (wire (path B.Cu 254 125730 -39370 125766 -39370 125791 -39395.4 126403 -39395.4)(net SS0)(type protect)) + (wire (path B.Cu 254 123190 -39370 125730 -39370)(net SS0)(type protect)) + (wire (path B.Cu 254 128270 -39370 128234 -39370 128209 -39395.4)(net SS0)(type protect)) + (wire (path B.Cu 254 129540 -40640 128270 -39370)(net SS0)(type protect)) + (wire (path B.Cu 254 117565 -39281 110401 -39281 110020 -38900)(net SCK)(type protect)) + (wire (path B.Cu 254 124365 -41814.7 124350 -41829)(net SCK)(type protect)) + (wire (path B.Cu 254 120113 -41829 117565 -39281)(net SCK)(type protect)) + (wire (path B.Cu 254 124350 -41829 120113 -41829)(net SCK)(type protect)) + (wire (path B.Cu 254 110020 -38900 109220 -38100)(net SCK)(type protect)) + (wire (path B.Cu 254 124460 -41910 124365 -41814.7)(net SCK)(type protect)) + (wire (path B.Cu 254 125730 -43180 124365 -41814.7)(net SCK)(type protect)) + (wire (path B.Cu 254 127000 -43180 125730 -43180)(net SCK)(type protect)) + (wire (path F.Cu 254 100059 -39058.8 99060 -38059.4)(net SCK)(type protect)) + (wire (path F.Cu 254 109220 -38100 106142 -38100 104803 -39439.9 100440 -39439.9 + 100059 -39058.8)(net SCK)(type protect)) + (wire (path F.Cu 254 113030 -39370 114000 -38400)(net MOSI)(type protect)) + (wire (path F.Cu 254 105591 -39370 113030 -39370)(net MOSI)(type protect)) + (wire (path F.Cu 254 91113.1 -41229 103732 -41229)(net MOSI)(type protect)) + (wire (path F.Cu 254 90759 -41583.1 91113.1 -41229)(net MOSI)(type protect)) + (wire (path F.Cu 254 103732 -41229 105591 -39370)(net MOSI)(type protect)) + (wire (path F.Cu 254 93980 -48219.4 90759 -44998.4 90759 -41583.1)(net MOSI)(type protect)) + (wire (path B.Cu 254 119969 -40966.9 119969 -38689)(net MOSI)(type protect)) + (wire (path B.Cu 254 117640 -36360 116840 -35560)(net MOSI)(type protect)) + (wire (path B.Cu 254 119969 -38689 117640 -36360)(net MOSI)(type protect)) + (wire (path B.Cu 254 124416 -41148 121150 -41148)(net MOSI)(type protect)) + (wire (path B.Cu 254 125153 -41884.6 124416 -41148)(net MOSI)(type protect)) + (wire (path B.Cu 254 128245 -41884.6 125153 -41884.6)(net MOSI)(type protect)) + (wire (path B.Cu 254 120323 -41321 119969 -40966.9)(net MOSI)(type protect)) + (wire (path B.Cu 254 129540 -43180 128245 -41884.6)(net MOSI)(type protect)) + (wire (path B.Cu 254 120977 -41321 120323 -41321)(net MOSI)(type protect)) + (wire (path B.Cu 254 121150 -41148 120977 -41321)(net MOSI)(type protect)) + (wire (path B.Cu 254 115570 -35560 114300 -36830)(net MOSI)(type protect)) + (wire (path B.Cu 254 116840 -35560 115570 -35560)(net MOSI)(type protect)) + (wire (path B.Cu 254 114300 -36830 114300 -38100)(net MOSI)(type protect)) + (wire (path F.Cu 254 114000 -38400 114000 -38400 114300 -38100)(net MOSI)(type protect)) + (wire (path F.Cu 254 113330 -39070 114000 -38400)(net MOSI)(type protect)) + (wire (path F.Cu 254 112960 -39439.9 113030 -39370 113330 -39070)(net MOSI)(type protect)) + (wire (path F.Cu 254 114300 -38100 114300 -38100)(net MOSI)(type protect)) + (wire (path F.Cu 254 123871 -42591 126136 -44856.4)(net MISO)(type protect)) + (wire (path F.Cu 254 109220 -35560 110909 -33871 119969 -33871 123871 -37773.1 + 123871 -42591)(net MISO)(type protect)) + (wire (path F.Cu 254 126136 -44856.4 127000 -45720)(net MISO)(type protect)) + (wire (path F.Cu 254 109220 -35560 96479.4 -35560 93980 -38059.4)(net MISO)(type protect)) + (wire (path F.Cu 254 96520 -54610 99060 -52070)(net "/RF433-OUT")(type protect)) + (wire (path F.Cu 254 96520 -55880 96520 -54610)(net "/RF433-OUT")(type protect)) + (wire (path B.Cu 254 99484.3 -52070 99060 -52070)(net "/RF433-OUT")(type protect)) + (wire (path B.Cu 254 105410 -52070 99484.3 -52070)(net "/RF433-OUT")(type protect)) + (wire (path B.Cu 254 109220 -48260 105410 -52070)(net "/RF433-OUT")(type protect)) + (wire (path F.Cu 254 99060 -55880 104140 -55880)(net "Net-(P4-Pad4)")(type protect)) + (wire (path B.Cu 254 120891 -47079 124460 -50647.6)(net "Net-(IC1-Pad12)")(type protect)) + (wire (path B.Cu 254 114777 -47079 120891 -47079)(net "Net-(IC1-Pad12)")(type protect)) + (wire (path B.Cu 254 124460 -50647.6 124460 -50800)(net "Net-(IC1-Pad12)")(type protect)) + (wire (path B.Cu 254 109220 -45720 113418 -45720 114777 -47079)(net "Net-(IC1-Pad12)")(type protect)) + (wire (path B.Cu 254 110351 -43180 109220 -43180)(net "Net-(IC1-Pad11)")(type protect)) + (wire (path B.Cu 254 115092 -43180 110351 -43180)(net "Net-(IC1-Pad11)")(type protect)) + (wire (path B.Cu 254 120713 -44361 116273 -44361)(net "Net-(IC1-Pad11)")(type protect)) + (wire (path B.Cu 254 127000 -50647.6 120713 -44361)(net "Net-(IC1-Pad11)")(type protect)) + (wire (path B.Cu 254 127000 -50800 127000 -50647.6)(net "Net-(IC1-Pad11)")(type protect)) + (wire (path B.Cu 254 116273 -44361 115092 -43180)(net "Net-(IC1-Pad11)")(type protect)) + (wire (path B.Cu 254 110020 -41440 109220 -40640)(net "Net-(IC1-Pad10)")(type protect)) + (wire (path B.Cu 254 119902 -42337 119475 -41910 110490 -41910)(net "Net-(IC1-Pad10)")(type protect)) + (wire (path B.Cu 254 121229 -42337 119902 -42337)(net "Net-(IC1-Pad10)")(type protect)) + (wire (path B.Cu 254 129540 -50647.6 121229 -42337)(net "Net-(IC1-Pad10)")(type protect)) + (wire (path B.Cu 254 129540 -50800 129540 -50647.6)(net "Net-(IC1-Pad10)")(type protect)) + (wire (path B.Cu 254 110490 -41910 110020 -41440)(net "Net-(IC1-Pad10)")(type protect)) + (wire (path F.Cu 254 116840 -38100 120650 -38100 121920 -39370 121920 -46990 + 120650 -48260)(net "/RF433-IN")(type protect)) + (wire (path F.Cu 254 123127 -52109.6 126897 -55880 127000 -55880)(net "/RF433-IN")(type protect)) + (wire (path B.Cu 254 120650 -48260 120650 -49530 123127 -52006.6 123127 -52109.6)(net "/RF433-IN")(type protect)) + (wire (path F.Cu 254 127000 -55880 127000 -55727.6)(net "/RF433-IN")(type protect)) + (wire (path F.Cu 254 105139 -44217.6 104140 -43218.1)(net "Tiny-RESET")(type protect)) + (wire (path F.Cu 254 105283 -44361 105139 -44217.6)(net "Tiny-RESET")(type protect)) + (wire (path F.Cu 254 115659 -44361 105283 -44361)(net "Tiny-RESET")(type protect)) + (wire (path F.Cu 254 116840 -43180 115659 -44361)(net "Tiny-RESET")(type protect)) + (wire (path B.Cu 254 104140 -43218.1 102760 -44598.6 90359.2 -44598.6 84819.5 -39058.8 + 83820 -38059.4)(net "Tiny-RESET")(type protect)) + (wire (path B.Cu 254 104862 -44539 104295 -45106.6)(net TX)(type protect)) + (wire (path B.Cu 254 115659 -44539 104862 -44539)(net TX)(type protect)) + (wire (path B.Cu 254 75073.5 -38059.4 73660 -38059.4)(net TX)(type protect)) + (wire (path B.Cu 254 116840 -45720 115659 -44539)(net TX)(type protect)) + (wire (path B.Cu 254 104295 -45106.6 82655 -45106.6)(net TX)(type protect)) + (wire (path B.Cu 254 75607.8 -38059.4 75073.5 -38059.4)(net TX)(type protect)) + (wire (path B.Cu 254 82655 -45106.6 75607.8 -38059.4)(net TX)(type protect)) + (wire (path F.Cu 254 104140 -38059.4 105280 -36919 112941 -36919)(net SS1)(type protect)) + (wire (path F.Cu 254 113030 -36830 114630 -36830 115570 -37770)(net SS1)(type protect)) + (wire (path F.Cu 254 112941 -36919 113030 -36830)(net SS1)(type protect)) + (wire (path F.Cu 254 115570 -37770 115570 -39370 116840 -40640)(net SS1)(type protect)) + (wire (path B.Cu 254 78740 -38059.4 77359.5 -36678.9)(net RX)(type protect)) + (wire (path B.Cu 254 105020 -45807.6 106202 -46990)(net RX)(type protect)) + (wire (path B.Cu 254 77359.5 -36678.9 72997.4 -36678.9)(net RX)(type protect)) + (wire (path B.Cu 254 72279.5 -38722 72997.4 -39439.9 76269.9 -39439.9)(net RX)(type protect)) + (wire (path B.Cu 254 72997.4 -36678.9 72279.5 -37396.7)(net RX)(type protect)) + (wire (path B.Cu 254 113030 -48260 116840 -48260)(net RX)(type protect)) + (wire (path B.Cu 254 72279.5 -37396.7 72279.5 -38722)(net RX)(type protect)) + (wire (path B.Cu 254 76269.9 -39439.9 82637.6 -45807.6 105020 -45807.6)(net RX)(type protect)) + (wire (path B.Cu 254 106202 -46990 111760 -46990 113030 -48260)(net RX)(type protect)) + (via "Via[0-1]_600:400_um" 91440 -41910 (net CE)(type protect)) + (via "Via[0-1]_600:400_um" 120650 -40640 (net CE)(type protect)) + (via "Via[0-1]_600:400_um" 123190 -39370 (net SS0)(type protect)) + (via "Via[0-1]_600:400_um" 114300 -38100 (net MOSI)(type protect)) + (via "Via[0-1]_600:400_um" 99060 -52070 (net "/RF433-OUT")(type protect)) + (via "Via[0-1]_600:400_um" 123127 -52109.6 (net "/RF433-IN")(type protect)) + (via "Via[0-1]_600:400_um" 120650 -48260 (net "/RF433-IN")(type protect)) + ) +) diff --git a/domopi.kicad_pcb b/domopi.kicad_pcb new file mode 100644 index 0000000..8683253 --- /dev/null +++ b/domopi.kicad_pcb @@ -0,0 +1,835 @@ +(kicad_pcb (version 4) (host pcbnew 4.0.1-3.201602080046+6200~38~ubuntu15.04.1-stable) + + (general + (links 37) + (no_connects 0) + (area 55.829287 20.645 119.048601 50.954001) + (thickness 1.6) + (drawings 8) + (tracks 155) + (zones 0) + (modules 11) + (nets 47) + ) + + (page A4) + (layers + (0 Top signal) + (31 Bottom signal) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.254) + (trace_clearance 0.1524) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.1524) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.6858) + (via_drill 0.3302) + (via_min_size 0.6858) + (via_min_drill 0.3302) + (uvia_size 0.762) + (uvia_drill 0.508) + (uvias_allowed no) + (uvia_min_size 0) + (uvia_min_drill 0) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 3 3) + (pad_drill 2) + (pad_to_mask_clearance 0.2) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010f0_80000001) + (usegerberextensions true) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 +3V3) + (net 3 +5V) + (net 4 CE) + (net 5 SS0) + (net 6 SCK) + (net 7 MOSI) + (net 8 MISO) + (net 9 /RF433-OUT) + (net 10 /RF433-IN) + (net 11 Tiny-RESET) + (net 12 TX) + (net 13 SS1) + (net 14 RX) + (net 15 /ADC3) + (net 16 /ADC2) + (net 17 /ADC1) + (net 18 /ANT) + (net 19 "Net-(P1-Pad1)") + (net 20 "Net-(P1-Pad3)") + (net 21 "Net-(P1-Pad5)") + (net 22 "Net-(P1-Pad7)") + (net 23 "Net-(P1-Pad9)") + (net 24 "Net-(P1-Pad11)") + (net 25 "Net-(P1-Pad12)") + (net 26 "Net-(P1-Pad13)") + (net 27 "Net-(P1-Pad14)") + (net 28 "Net-(P1-Pad16)") + (net 29 "Net-(P1-Pad25)") + (net 30 "Net-(P1-Pad26)") + (net 31 "Net-(P1-Pad27)") + (net 32 "Net-(P1-Pad28)") + (net 33 "Net-(P1-Pad29)") + (net 34 "Net-(P1-Pad30)") + (net 35 "Net-(P1-Pad31)") + (net 36 "Net-(P1-Pad32)") + (net 37 "Net-(P1-Pad33)") + (net 38 "Net-(P1-Pad34)") + (net 39 "Net-(P1-Pad35)") + (net 40 "Net-(P1-Pad36)") + (net 41 "Net-(P1-Pad37)") + (net 42 "Net-(P1-Pad38)") + (net 43 "Net-(P1-Pad39)") + (net 44 "Net-(P1-Pad40)") + (net 45 /NRF-INT) + (net 46 "Net-(P7-Pad2)") + + (net_class Default "This is the default net class." + (clearance 0.1524) + (trace_width 0.254) + (via_dia 0.6858) + (via_drill 0.3302) + (uvia_dia 0.762) + (uvia_drill 0.508) + (add_net /ADC1) + (add_net /ADC2) + (add_net /ADC3) + (add_net /NRF-INT) + (add_net /RF433-IN) + (add_net /RF433-OUT) + (add_net CE) + (add_net MISO) + (add_net MOSI) + (add_net "Net-(P1-Pad1)") + (add_net "Net-(P1-Pad11)") + (add_net "Net-(P1-Pad12)") + (add_net "Net-(P1-Pad13)") + (add_net "Net-(P1-Pad14)") + (add_net "Net-(P1-Pad16)") + (add_net "Net-(P1-Pad25)") + (add_net "Net-(P1-Pad26)") + (add_net "Net-(P1-Pad27)") + (add_net "Net-(P1-Pad28)") + (add_net "Net-(P1-Pad29)") + (add_net "Net-(P1-Pad3)") + (add_net "Net-(P1-Pad30)") + (add_net "Net-(P1-Pad31)") + (add_net "Net-(P1-Pad32)") + (add_net "Net-(P1-Pad33)") + (add_net "Net-(P1-Pad34)") + (add_net "Net-(P1-Pad35)") + (add_net "Net-(P1-Pad36)") + (add_net "Net-(P1-Pad37)") + (add_net "Net-(P1-Pad38)") + (add_net "Net-(P1-Pad39)") + (add_net "Net-(P1-Pad40)") + (add_net "Net-(P1-Pad5)") + (add_net "Net-(P1-Pad7)") + (add_net "Net-(P1-Pad9)") + (add_net "Net-(P7-Pad2)") + (add_net RX) + (add_net SCK) + (add_net SS0) + (add_net SS1) + (add_net TX) + (add_net Tiny-RESET) + ) + + (net_class ANT "" + (clearance 0.254) + (trace_width 0.508) + (via_dia 0.6858) + (via_drill 0.3302) + (uvia_dia 0.762) + (uvia_drill 0.508) + (add_net /ANT) + ) + + (net_class Power "" + (clearance 0.254) + (trace_width 0.4064) + (via_dia 0.6858) + (via_drill 0.3302) + (uvia_dia 0.762) + (uvia_drill 0.508) + (add_net +3V3) + (add_net +5V) + (add_net GND) + ) + + (module Capacitors_Elko_ThroughHole:Elko_vert_11.2x6.3mm_RM2.5 (layer Top) (tedit 560CF65C) (tstamp 560BF081) + (at 116.84 36.195 180) + (descr "Electrolytic Capacitor, vertical, diameter 6,3mm, RM 2,5mm, radial,") + (tags "Electrolytic Capacitor, vertical, diameter 6,3mm, RM 2,5mm, Elko, Electrolytkondensator, Kondensator gepolt, Durchmesser 6,3mm, radial,") + (path /560C23BB) + (fp_text reference C3 (at 2.54 1.651 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 10u (at 1.27 5.08 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.26924 -2.19964) (end 0.26924 -1.19888) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.23114 -1.69926) (end 0.76962 -1.69926) (layer F.SilkS) (width 0.15)) + (fp_circle (center 1.27 0) (end 4.4196 0) (layer F.SilkS) (width 0.15)) + (pad 2 thru_hole circle (at 2.54 0 180) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 2 +3V3)) + (pad 1 thru_hole circle (at 0 0 180) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (model Capacitors_Elko_ThroughHole.3dshapes/Elko_vert_11.2x6.3mm_RM2.5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitors_Elko_ThroughHole:Elko_vert_11.2x6.3mm_RM2.5 (layer Top) (tedit 560CF933) (tstamp 560BF086) + (at 81.28 43.815 90) + (descr "Electrolytic Capacitor, vertical, diameter 6,3mm, RM 2,5mm, radial,") + (tags "Electrolytic Capacitor, vertical, diameter 6,3mm, RM 2,5mm, Elko, Electrolytkondensator, Kondensator gepolt, Durchmesser 6,3mm, radial,") + (path /560D0C56) + (fp_text reference C4 (at 3.429 1.778 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 10u (at 0.381 1.778 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.26924 -2.19964) (end 0.26924 -1.19888) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.23114 -1.69926) (end 0.76962 -1.69926) (layer F.SilkS) (width 0.15)) + (fp_circle (center 1.27 0) (end 4.4196 0) (layer F.SilkS) (width 0.15)) + (pad 2 thru_hole circle (at 2.54 0 90) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (pad 1 thru_hole circle (at 0 0 90) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 3 +5V)) + (model Capacitors_Elko_ThroughHole.3dshapes/Elko_vert_11.2x6.3mm_RM2.5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Socket_Strips:Socket_Strip_Straight_2x20 (layer Bottom) (tedit 560CF9B1) (tstamp 560BDFDF) + (at 68.58 30.48) + (descr "Through hole socket strip") + (tags "socket strip") + (path /560BE092) + (fp_text reference P1 (at 0.254 2.54) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_text value RASPBERRY (at 45.085 2.54) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_line (start -1.75 1.75) (end -1.75 -4.3) (layer B.CrtYd) (width 0.05)) + (fp_line (start 50.05 1.75) (end 50.05 -4.3) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.75 1.75) (end 50.05 1.75) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.75 -4.3) (end 50.05 -4.3) (layer B.CrtYd) (width 0.05)) + (fp_line (start 49.53 -3.81) (end -1.27 -3.81) (layer B.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 49.53 1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start 49.53 -3.81) (end 49.53 1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start -1.27 -3.81) (end -1.27 -1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start 0 1.55) (end -1.55 1.55) (layer B.SilkS) (width 0.15)) + (fp_line (start -1.27 -1.27) (end 1.27 -1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start -1.55 1.55) (end -1.55 0) (layer B.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 19 "Net-(P1-Pad1)")) + (pad 2 thru_hole oval (at 0 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 3 +5V)) + (pad 3 thru_hole oval (at 2.54 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 20 "Net-(P1-Pad3)")) + (pad 4 thru_hole oval (at 2.54 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 3 +5V)) + (pad 5 thru_hole oval (at 5.08 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 21 "Net-(P1-Pad5)")) + (pad 6 thru_hole oval (at 5.08 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 1 GND)) + (pad 7 thru_hole oval (at 7.62 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 22 "Net-(P1-Pad7)")) + (pad 8 thru_hole oval (at 7.62 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 12 TX)) + (pad 9 thru_hole oval (at 10.16 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 23 "Net-(P1-Pad9)")) + (pad 10 thru_hole oval (at 10.16 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 14 RX)) + (pad 11 thru_hole oval (at 12.7 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 24 "Net-(P1-Pad11)")) + (pad 12 thru_hole oval (at 12.7 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 25 "Net-(P1-Pad12)")) + (pad 13 thru_hole oval (at 15.24 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 26 "Net-(P1-Pad13)")) + (pad 14 thru_hole oval (at 15.24 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 27 "Net-(P1-Pad14)")) + (pad 15 thru_hole oval (at 17.78 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 11 Tiny-RESET)) + (pad 16 thru_hole oval (at 17.78 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 28 "Net-(P1-Pad16)")) + (pad 17 thru_hole oval (at 20.32 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 2 +3V3)) + (pad 18 thru_hole oval (at 20.32 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 4 CE)) + (pad 19 thru_hole oval (at 22.86 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 7 MOSI)) + (pad 20 thru_hole oval (at 22.86 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 1 GND)) + (pad 21 thru_hole oval (at 25.4 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 8 MISO)) + (pad 22 thru_hole oval (at 25.4 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 5 SS0)) + (pad 23 thru_hole oval (at 27.94 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 6 SCK)) + (pad 24 thru_hole oval (at 27.94 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 13 SS1)) + (pad 25 thru_hole oval (at 30.48 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 29 "Net-(P1-Pad25)")) + (pad 26 thru_hole oval (at 30.48 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 30 "Net-(P1-Pad26)")) + (pad 27 thru_hole oval (at 33.02 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 31 "Net-(P1-Pad27)")) + (pad 28 thru_hole oval (at 33.02 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 32 "Net-(P1-Pad28)")) + (pad 29 thru_hole oval (at 35.56 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 33 "Net-(P1-Pad29)")) + (pad 30 thru_hole oval (at 35.56 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 34 "Net-(P1-Pad30)")) + (pad 31 thru_hole oval (at 38.1 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 35 "Net-(P1-Pad31)")) + (pad 32 thru_hole oval (at 38.1 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 36 "Net-(P1-Pad32)")) + (pad 33 thru_hole oval (at 40.64 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 37 "Net-(P1-Pad33)")) + (pad 34 thru_hole oval (at 40.64 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 38 "Net-(P1-Pad34)")) + (pad 35 thru_hole oval (at 43.18 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 39 "Net-(P1-Pad35)")) + (pad 36 thru_hole oval (at 43.18 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 40 "Net-(P1-Pad36)")) + (pad 37 thru_hole oval (at 45.72 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 41 "Net-(P1-Pad37)")) + (pad 38 thru_hole oval (at 45.72 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 42 "Net-(P1-Pad38)")) + (pad 39 thru_hole oval (at 48.26 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 43 "Net-(P1-Pad39)")) + (pad 40 thru_hole oval (at 48.26 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 44 "Net-(P1-Pad40)")) + (model Socket_Strips.3dshapes/Socket_Strip_Straight_2x20.wrl + (at (xyz 0.95 -0.05 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x02 (layer Top) (tedit 560CF25E) (tstamp 560BDFE5) + (at 68.58 40.64 180) + (descr "Through hole pin header") + (tags "pin header") + (path /560C2BF5) + (fp_text reference P2 (at -2.794 3.302 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X02 (at 0 -3.1 180) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.27 1.27) (end 1.27 3.81) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.55 -1.55) (end 1.55 0) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.75 -1.75) (end -1.75 4.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.75 -1.75) (end 1.75 4.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 4.3) (end 1.75 4.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.27 1.27) (end -1.27 3.81) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.27 3.81) (end 1.27 3.81) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 3 +5V)) + (pad 2 thru_hole oval (at 0 2.54 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_1x02.wrl + (at (xyz 0 -0.05 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Housings_DIP:DIP-14_W7.62mm (layer Top) (tedit 560CF929) (tstamp 560BE100) + (at 103.505 36.83 270) + (descr "14-lead dip package, row spacing 7.62 mm (300 mils)") + (tags "dil dip 2.54 300") + (path /560BE23A) + (fp_text reference IC1 (at 5.588 -1.397 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value ATTINY84A-P (at 3.81 7.62 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.05 -2.45) (end -1.05 17.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.65 -2.45) (end 8.65 17.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 -2.45) (end 8.65 -2.45) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 17.7) (end 8.65 17.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.135 -2.295) (end 0.135 -1.025) (layer F.SilkS) (width 0.15)) + (fp_line (start 7.485 -2.295) (end 7.485 -1.025) (layer F.SilkS) (width 0.15)) + (fp_line (start 7.485 17.535) (end 7.485 16.265) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.135 17.535) (end 0.135 16.265) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.135 -2.295) (end 7.485 -2.295) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.135 17.535) (end 7.485 17.535) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.135 -1.025) (end -0.8 -1.025) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole oval (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 2 +3V3)) + (pad 2 thru_hole oval (at 0 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 14 RX)) + (pad 3 thru_hole oval (at 0 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 12 TX)) + (pad 4 thru_hole oval (at 0 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 11 Tiny-RESET)) + (pad 5 thru_hole oval (at 0 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 13 SS1)) + (pad 6 thru_hole oval (at 0 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 10 /RF433-IN)) + (pad 7 thru_hole oval (at 0 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 7 MOSI)) + (pad 8 thru_hole oval (at 7.62 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 8 MISO)) + (pad 9 thru_hole oval (at 7.62 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 6 SCK)) + (pad 10 thru_hole oval (at 7.62 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 15 /ADC3)) + (pad 11 thru_hole oval (at 7.62 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 16 /ADC2)) + (pad 12 thru_hole oval (at 7.62 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 17 /ADC1)) + (pad 13 thru_hole oval (at 7.62 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 9 /RF433-OUT)) + (pad 14 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (model Housings_DIP.3dshapes/DIP-14_W7.62mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistors_ThroughHole:Resistor_Vertical_RM5mm (layer Top) (tedit 560CF953) (tstamp 560BF1E3) + (at 77.47 34.925) + (descr "Resistor, Vertical, RM 5mm, 1/3W,") + (tags "Resistor, Vertical, RM 5mm, 1/3W,") + (path /560CAD51) + (fp_text reference R10 (at -5.08 -0.381) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 4.7k (at -3.302 -1.651) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.09906 0) (end 0.9017 0) (layer F.SilkS) (width 0.15)) + (fp_circle (center -2.49936 0) (end 0 0) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole circle (at -2.49936 0) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 2 +3V3)) + (pad 2 thru_hole circle (at 2.5019 0) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 11 Tiny-RESET)) + ) + + (module Socket_Strips:Socket_Strip_Straight_1x04 (layer Top) (tedit 560CF96E) (tstamp 560BFC1B) + (at 78.105 48.26 180) + (descr "Through hole socket strip") + (tags "socket strip") + (path /560D0649) + (fp_text reference P4 (at -0.889 2.286 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value RFTX (at -3.175 0.635 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.75 -1.75) (end -1.75 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 9.4 -1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 9.4 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 -1.27) (end 8.89 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 1.55) (end 0 1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start 8.89 -1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end -1.55 1.55) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 3 +5V)) + (pad 2 thru_hole oval (at 2.54 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (pad 3 thru_hole oval (at 5.08 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 9 /RF433-OUT)) + (pad 4 thru_hole oval (at 7.62 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 18 /ANT)) + (model Socket_Strips.3dshapes/Socket_Strip_Straight_1x04.wrl + (at (xyz 0.15 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Socket_Strips:Socket_Strip_Straight_1x04 (layer Top) (tedit 560CF969) (tstamp 560BFC28) + (at 97.155 48.26 180) + (descr "Through hole socket strip") + (tags "socket strip") + (path /560D0737) + (fp_text reference P7 (at 8.001 2.032 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value RFRX (at 10.795 0.635 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.75 -1.75) (end -1.75 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 9.4 -1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 9.4 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 -1.27) (end 8.89 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 1.55) (end 0 1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start 8.89 -1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end -1.55 1.55) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 3 +5V)) + (pad 2 thru_hole oval (at 2.54 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 46 "Net-(P7-Pad2)")) + (pad 3 thru_hole oval (at 5.08 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 10 /RF433-IN)) + (pad 4 thru_hole oval (at 7.62 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (model Socket_Strips.3dshapes/Socket_Strip_Straight_1x04.wrl + (at (xyz 0.15 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_2x04 (layer Top) (tedit 560CF95F) (tstamp 560BFE6B) + (at 114.3 41.275) + (descr "Through hole pin header") + (tags "pin header") + (path /560BE537) + (fp_text reference P3 (at -2.794 -0.889) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value nRF24L01P (at -0.762 -2.413) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.75 -1.75) (end -1.75 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.3 -1.75) (end 4.3 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 4.3 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 9.4) (end 4.3 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.27 1.27) (end -1.27 8.89) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.27 8.89) (end 3.81 8.89) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.81 8.89) (end 3.81 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.81 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 2 +3V3)) + (pad 2 thru_hole oval (at 2.54 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (pad 3 thru_hole oval (at 0 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 4 CE)) + (pad 4 thru_hole oval (at 2.54 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 5 SS0)) + (pad 5 thru_hole oval (at 0 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 6 SCK)) + (pad 6 thru_hole oval (at 2.54 5.08) (size 1.7272 1.7272) (drill 1.016) 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70.485 46.355) (width 0.508) (layer Top) (net 18)) + (segment (start 70.485 46.355) (end 74.295 42.545) (width 0.508) (layer Top) (net 18)) + +) diff --git a/domopi.kicad_pcb-bak b/domopi.kicad_pcb-bak new file mode 100644 index 0000000..73910ab --- /dev/null +++ b/domopi.kicad_pcb-bak @@ -0,0 +1,764 @@ +(kicad_pcb (version 4) (host pcbnew "(2015-09-28 BZR 6225)-product") + + (general + (links 37) + (no_connects 0) + (area 55.829287 20.645 119.048601 50.954001) + (thickness 1.6) + (drawings 8) + (tracks 144) + (zones 0) + (modules 11) + (nets 19) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user hide) + (33 F.Adhes user hide) + (34 B.Paste user hide) + (35 F.Paste user hide) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user hide) + (39 F.Mask user hide) + (40 Dwgs.User user hide) + (41 Cmts.User user hide) + (42 Eco1.User user hide) + (43 Eco2.User user hide) + (44 Edge.Cuts user) + (45 Margin user hide) + (46 B.CrtYd user hide) + (47 F.CrtYd user hide) + (48 B.Fab user hide) + (49 F.Fab user hide) + ) + + (setup + (last_trace_width 0.254) + (trace_clearance 0.254) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.1524) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.6) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3302) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0) + (uvia_min_drill 0) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.2) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010f0_80000001) + (usegerberextensions false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15) + (hpglpenoverlay 2) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 0) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 GND) + (net 2 +3V3) + (net 3 +5V) + (net 4 CE) + (net 5 SS0) + (net 6 SCK) + (net 7 MOSI) + (net 8 MISO) + (net 9 /RF433-OUT) + (net 10 /RF433-IN) + (net 11 Tiny-RESET) + (net 12 TX) + (net 13 SS1) + (net 14 RX) + (net 15 /ADC3) + (net 16 /ADC2) + (net 17 /ADC1) + (net 18 /ANT) + + (net_class Default "This is the default net class." + (clearance 0.254) + (trace_width 0.254) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net /ADC1) + (add_net /ADC2) + (add_net /ADC3) + (add_net /RF433-IN) + (add_net /RF433-OUT) + (add_net CE) + (add_net MISO) + (add_net MOSI) + (add_net RX) + (add_net SCK) + (add_net SS0) + (add_net SS1) + (add_net TX) + (add_net Tiny-RESET) + ) + + (net_class ANT "" + (clearance 0.254) + (trace_width 0.4064) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net /ANT) + ) + + (net_class Power "" + (clearance 0.254) + (trace_width 0.4064) + (via_dia 0.6) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net +3V3) + (add_net +5V) + (add_net GND) + ) + + (module Capacitors_Elko_ThroughHole:Elko_vert_11.2x6.3mm_RM2.5 (layer F.Cu) (tedit 560CF65C) (tstamp 560BF081) + (at 116.84 36.195 180) + (descr "Electrolytic Capacitor, vertical, diameter 6,3mm, RM 2,5mm, radial,") + (tags "Electrolytic Capacitor, vertical, diameter 6,3mm, RM 2,5mm, Elko, Electrolytkondensator, Kondensator gepolt, Durchmesser 6,3mm, radial,") + (path /560C23BB) + (fp_text reference C3 (at 2.54 1.651 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 10u (at 1.27 5.08 180) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.26924 -2.19964) (end 0.26924 -1.19888) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.23114 -1.69926) (end 0.76962 -1.69926) (layer F.SilkS) (width 0.15)) + (fp_circle (center 1.27 0) (end 4.4196 0) (layer F.SilkS) (width 0.15)) + (pad 2 thru_hole circle (at 2.54 0 180) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 2 +3V3)) + (pad 1 thru_hole circle (at 0 0 180) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (model Capacitors_Elko_ThroughHole.3dshapes/Elko_vert_11.2x6.3mm_RM2.5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitors_Elko_ThroughHole:Elko_vert_11.2x6.3mm_RM2.5 (layer F.Cu) (tedit 560CF933) (tstamp 560BF086) + (at 78.105 41.91 180) + (descr "Electrolytic Capacitor, vertical, diameter 6,3mm, RM 2,5mm, radial,") + (tags "Electrolytic Capacitor, vertical, diameter 6,3mm, RM 2,5mm, Elko, Electrolytkondensator, Kondensator gepolt, Durchmesser 6,3mm, radial,") + (path /560D0C56) + (fp_text reference C4 (at 3.429 1.778 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 10u (at 0.381 1.778 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 0.26924 -2.19964) (end 0.26924 -1.19888) (layer F.SilkS) (width 0.15)) + (fp_line (start -0.23114 -1.69926) (end 0.76962 -1.69926) (layer F.SilkS) (width 0.15)) + (fp_circle (center 1.27 0) (end 4.4196 0) (layer F.SilkS) (width 0.15)) + (pad 2 thru_hole circle (at 2.54 0 180) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (pad 1 thru_hole circle (at 0 0 180) (size 1.50114 1.50114) (drill 0.8001) (layers *.Cu *.Mask F.SilkS) + (net 3 +5V)) + (model Capacitors_Elko_ThroughHole.3dshapes/Elko_vert_11.2x6.3mm_RM2.5.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Socket_Strips:Socket_Strip_Straight_2x20 (layer B.Cu) (tedit 560CF9B1) (tstamp 560BDFDF) + (at 68.58 30.48) + (descr "Through hole socket strip") + (tags "socket strip") + (path /560BE092) + (fp_text reference P1 (at 0.254 2.54) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_text value RASPBERRY (at 45.085 2.54) (layer B.SilkS) + (effects (font (size 1 1) (thickness 0.15)) (justify mirror)) + ) + (fp_line (start -1.75 1.75) (end -1.75 -4.3) (layer B.CrtYd) (width 0.05)) + (fp_line (start 50.05 1.75) (end 50.05 -4.3) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.75 1.75) (end 50.05 1.75) (layer B.CrtYd) (width 0.05)) + (fp_line (start -1.75 -4.3) (end 50.05 -4.3) (layer B.CrtYd) (width 0.05)) + (fp_line (start 49.53 -3.81) (end -1.27 -3.81) (layer B.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 49.53 1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start 49.53 -3.81) (end 49.53 1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start -1.27 -3.81) (end -1.27 -1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start 0 1.55) (end -1.55 1.55) (layer B.SilkS) (width 0.15)) + (fp_line (start -1.27 -1.27) (end 1.27 -1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer B.SilkS) (width 0.15)) + (fp_line (start -1.55 1.55) (end -1.55 0) (layer B.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 2 thru_hole oval (at 0 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 3 +5V)) + (pad 3 thru_hole oval (at 2.54 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 4 thru_hole oval (at 2.54 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 3 +5V)) + (pad 5 thru_hole oval (at 5.08 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 6 thru_hole oval (at 5.08 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 1 GND)) + (pad 7 thru_hole oval (at 7.62 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 8 thru_hole oval (at 7.62 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 12 TX)) + (pad 9 thru_hole oval (at 10.16 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 10 thru_hole oval (at 10.16 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 14 RX)) + (pad 11 thru_hole oval (at 12.7 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 12 thru_hole oval (at 12.7 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 13 thru_hole oval (at 15.24 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 14 thru_hole oval (at 15.24 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 15 thru_hole oval (at 17.78 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 11 Tiny-RESET)) + (pad 16 thru_hole oval (at 17.78 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 17 thru_hole oval (at 20.32 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 2 +3V3)) + (pad 18 thru_hole oval (at 20.32 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 4 CE)) + (pad 19 thru_hole oval (at 22.86 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 7 MOSI)) + (pad 20 thru_hole oval (at 22.86 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 1 GND)) + (pad 21 thru_hole oval (at 25.4 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 8 MISO)) + (pad 22 thru_hole oval (at 25.4 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 5 SS0)) + (pad 23 thru_hole oval (at 27.94 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 6 SCK)) + (pad 24 thru_hole oval (at 27.94 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS) + (net 13 SS1)) + (pad 25 thru_hole oval (at 30.48 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 26 thru_hole oval (at 30.48 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 27 thru_hole oval (at 33.02 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 28 thru_hole oval (at 33.02 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 29 thru_hole oval (at 35.56 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 30 thru_hole oval (at 35.56 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 31 thru_hole oval (at 38.1 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 32 thru_hole oval (at 38.1 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 33 thru_hole oval (at 40.64 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 34 thru_hole oval (at 40.64 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 35 thru_hole oval (at 43.18 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 36 thru_hole oval (at 43.18 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 37 thru_hole oval (at 45.72 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 38 thru_hole oval (at 45.72 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 39 thru_hole oval (at 48.26 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (pad 40 thru_hole oval (at 48.26 -2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)) + (model Socket_Strips.3dshapes/Socket_Strip_Straight_2x20.wrl + (at (xyz 0.95 -0.05 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x02 (layer F.Cu) (tedit 560CF25E) (tstamp 560BDFE5) + (at 68.58 40.64 180) + (descr "Through hole pin header") + (tags "pin header") + (path /560C2BF5) + (fp_text reference P2 (at -2.794 3.302 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value CONN_01X02 (at 0 -3.1 180) (layer F.Fab) hide + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.27 1.27) (end 1.27 3.81) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.55 -1.55) (end 1.55 0) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.75 -1.75) (end -1.75 4.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.75 -1.75) (end 1.75 4.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 4.3) (end 1.75 4.3) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.27 1.27) (end -1.27 3.81) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.27 3.81) (end 1.27 3.81) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 3 +5V)) + (pad 2 thru_hole oval (at 0 2.54 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_1x02.wrl + (at (xyz 0 -0.05 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_1x01 (layer F.Cu) (tedit 560CF985) (tstamp 560BDFFE) + (at 70.485 45.085) + (descr "Through hole pin header") + (tags "pin header") + (path /560D11E1) + (fp_text reference P5 (at 0.635 -2.413) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value ANT (at 2.921 0.635) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 1.55 -1.55) (end 1.55 0) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.75 -1.75) (end -1.75 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.75 -1.75) (end 1.75 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 1.75) (end 1.75 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.55 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0) (size 2.2352 2.2352) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 18 /ANT)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_1x01.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Housings_DIP:DIP-14_W7.62mm (layer F.Cu) (tedit 560CF929) (tstamp 560BE100) + (at 103.505 36.83 270) + (descr "14-lead dip package, row spacing 7.62 mm (300 mils)") + (tags "dil dip 2.54 300") + (path /560BE23A) + (fp_text reference IC1 (at 5.588 -1.397 270) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value ATTINY84A-P (at 3.81 7.62 360) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.05 -2.45) (end -1.05 17.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 8.65 -2.45) (end 8.65 17.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 -2.45) (end 8.65 -2.45) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.05 17.7) (end 8.65 17.7) (layer F.CrtYd) (width 0.05)) + (fp_line (start 0.135 -2.295) (end 0.135 -1.025) (layer F.SilkS) (width 0.15)) + (fp_line (start 7.485 -2.295) (end 7.485 -1.025) (layer F.SilkS) (width 0.15)) + (fp_line (start 7.485 17.535) (end 7.485 16.265) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.135 17.535) (end 0.135 16.265) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.135 -2.295) (end 7.485 -2.295) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.135 17.535) (end 7.485 17.535) (layer F.SilkS) (width 0.15)) + (fp_line (start 0.135 -1.025) (end -0.8 -1.025) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole oval (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 2 +3V3)) + (pad 2 thru_hole oval (at 0 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 14 RX)) + (pad 3 thru_hole oval (at 0 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 12 TX)) + (pad 4 thru_hole oval (at 0 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 11 Tiny-RESET)) + (pad 5 thru_hole oval (at 0 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 13 SS1)) + (pad 6 thru_hole oval (at 0 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 10 /RF433-IN)) + (pad 7 thru_hole oval (at 0 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 7 MOSI)) + (pad 8 thru_hole oval (at 7.62 15.24 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 8 MISO)) + (pad 9 thru_hole oval (at 7.62 12.7 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 6 SCK)) + (pad 10 thru_hole oval (at 7.62 10.16 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 15 /ADC3)) + (pad 11 thru_hole oval (at 7.62 7.62 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 16 /ADC2)) + (pad 12 thru_hole oval (at 7.62 5.08 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 17 /ADC1)) + (pad 13 thru_hole oval (at 7.62 2.54 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 9 /RF433-OUT)) + (pad 14 thru_hole oval (at 7.62 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (model Housings_DIP.3dshapes/DIP-14_W7.62mm.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistors_ThroughHole:Resistor_Vertical_RM5mm (layer F.Cu) (tedit 560CF953) (tstamp 560BF1E3) + (at 77.47 34.925) + (descr "Resistor, Vertical, RM 5mm, 1/3W,") + (tags "Resistor, Vertical, RM 5mm, 1/3W,") + (path /560CAD51) + (fp_text reference R10 (at -5.08 -0.381) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 4.7k (at -3.302 -1.651) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -0.09906 0) (end 0.9017 0) (layer F.SilkS) (width 0.15)) + (fp_circle (center -2.49936 0) (end 0 0) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole circle (at -2.49936 0) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 2 +3V3)) + (pad 2 thru_hole circle (at 2.5019 0) (size 1.99898 1.99898) (drill 1.00076) (layers *.Cu *.SilkS *.Mask) + (net 11 Tiny-RESET)) + ) + + (module Socket_Strips:Socket_Strip_Straight_1x04 (layer F.Cu) (tedit 560CF96E) (tstamp 560BFC1B) + (at 78.105 48.26 180) + (descr "Through hole socket strip") + (tags "socket strip") + (path /560D0649) + (fp_text reference P4 (at -0.889 2.286 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value RFTX (at -3.175 0.635 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.75 -1.75) (end -1.75 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 9.4 -1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 9.4 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 -1.27) (end 8.89 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 1.55) (end 0 1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start 8.89 -1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end -1.55 1.55) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 3 +5V)) + (pad 2 thru_hole oval (at 2.54 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (pad 3 thru_hole oval (at 5.08 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 9 /RF433-OUT)) + (pad 4 thru_hole oval (at 7.62 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 18 /ANT)) + (model Socket_Strips.3dshapes/Socket_Strip_Straight_1x04.wrl + (at (xyz 0.15 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Socket_Strips:Socket_Strip_Straight_1x04 (layer F.Cu) (tedit 560CF969) (tstamp 560BFC28) + (at 97.155 48.26 180) + (descr "Through hole socket strip") + (tags "socket strip") + (path /560D0737) + (fp_text reference P7 (at 8.001 2.032 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value RFRX (at 10.795 0.635 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.75 -1.75) (end -1.75 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 9.4 -1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 9.4 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 -1.27) (end 8.89 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 1.55) (end 0 1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start 8.89 -1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end -1.55 1.55) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 3 +5V)) + (pad 2 thru_hole oval (at 2.54 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS)) + (pad 3 thru_hole oval (at 5.08 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 10 /RF433-IN)) + (pad 4 thru_hole oval (at 7.62 0 180) (size 1.7272 2.032) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (model Socket_Strips.3dshapes/Socket_Strip_Straight_1x04.wrl + (at (xyz 0.15 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 180)) + ) + ) + + (module Pin_Headers:Pin_Header_Straight_2x04 (layer F.Cu) (tedit 560CF95F) (tstamp 560BFE6B) + (at 114.3 41.275) + (descr "Through hole pin header") + (tags "pin header") + (path /560BE537) + (fp_text reference P3 (at -2.794 -0.889) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value nRF24L01P (at -0.762 -2.413) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.75 -1.75) (end -1.75 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start 4.3 -1.75) (end 4.3 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 4.3 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 9.4) (end 4.3 9.4) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.27 1.27) (end -1.27 8.89) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.27 8.89) (end 3.81 8.89) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.81 8.89) (end 3.81 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 3.81 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 2 +3V3)) + (pad 2 thru_hole oval (at 2.54 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 1 GND)) + (pad 3 thru_hole oval (at 0 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 4 CE)) + (pad 4 thru_hole oval (at 2.54 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 5 SS0)) + (pad 5 thru_hole oval (at 0 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 6 SCK)) + (pad 6 thru_hole oval (at 2.54 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 7 MOSI)) + (pad 7 thru_hole oval (at 0 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS) + (net 8 MISO)) + (pad 8 thru_hole oval (at 2.54 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)) + (model Pin_Headers.3dshapes/Pin_Header_Straight_2x04.wrl + (at (xyz 0.05 -0.15 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 90)) + ) + ) + + (module Socket_Strips:Socket_Strip_Straight_1x04 (layer F.Cu) (tedit 560CF964) (tstamp 560CDEF5) + (at 109.855 48.26 180) + (descr "Through hole socket strip") + (tags "socket strip") + (path /560CF763) + (fp_text reference P6 (at 8.001 2.032 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value Sensors (at 1.27 2.54 180) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.75 -1.75) (end -1.75 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 9.4 -1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 -1.75) (end 9.4 -1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.75 1.75) (end 9.4 1.75) (layer F.CrtYd) (width 0.05)) + (fp_line (start 1.27 -1.27) (end 8.89 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 1.55) (end 0 1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start 8.89 -1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15)) + (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15)) + (fp_line (start -1.55 -1.55) (end -1.55 1.55) (layer F.SilkS) (width 0.15)) + (pad 1 thru_hole rect (at 0 0 180) (size 1.7272 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--- /dev/null +++ b/domopi.net @@ -0,0 +1,382 @@ +(export (version D) + (design + (source /home/arnaud/kicad/domopi/domopi.sch) + (date "lun. 08 févr. 2016 14:53:33 CET") + (tool "Eeschema 4.0.1-3.201602080046+6200~38~ubuntu15.04.1-stable") + (sheet (number 1) (name /) (tstamps /) + (title_block + (title) + (company) + (rev) + (date) + (source domopi.sch) + (comment (number 1) (value "")) + (comment (number 2) (value "")) + (comment (number 3) (value "")) + (comment (number 4) (value ""))))) + (components + (comp (ref IC1) + (value ATTINY84A-P) + (footprint Housings_DIP:DIP-14_W7.62mm) + (libsource (lib atmel) (part ATTINY84A-P)) + (sheetpath (names /) (tstamps /)) + (tstamp 560BE23A)) + (comp (ref P3) + (value nRF24L01P) + (footprint Pin_Headers:Pin_Header_Straight_2x04) + (libsource (lib conn) (part CONN_02X04)) + (sheetpath (names /) (tstamps /)) + (tstamp 560BE537)) + (comp (ref C3) + (value 10u) + (footprint Capacitors_Elko_ThroughHole:Elko_vert_11.2x6.3mm_RM2.5) + (libsource (lib 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(tstamp 560D0C56)) + (comp (ref P5) + (value ANT) + (footprint Wire_Pads:SolderWirePad_single_2mmDrill) + (libsource (lib conn) (part CONN_01X01)) + (sheetpath (names /) (tstamps /)) + (tstamp 560D11E1)) + (comp (ref P1) + (value RASPBERRY) + (footprint Socket_Strips:Socket_Strip_Straight_2x20) + (libsource (lib conn) (part CONN_02X20)) + (sheetpath (names /) (tstamps /)) + (tstamp 560BE092)) + (comp (ref P2) + (value CONN_01X02) + (footprint Pin_Headers:Pin_Header_Straight_1x02) + (libsource (lib conn) (part CONN_01X02)) + (sheetpath (names /) (tstamps /)) + (tstamp 560C2BF5))) + (libparts + (libpart (lib atmel) (part ATTINY24A-P) + (aliases + (alias ATTINY44A-P) + (alias ATTINY84A-P)) + (description "PDIP14, 2k Flash, 128B SRAM, 128B EEPROM, dW") + (docs http://www.atmel.com/Images/doc8183.pdf) + (fields + (field (name Reference) IC) + (field (name Value) ATTINY24A-P) + (field (name Footprint) DIP14)) + (pins + (pin (num 1) (name VCC) (type power_in)) + (pin (num 2) (name "(PCINT8/CLKI/XTAL1)PB0") (type BiDi)) + (pin (num 3) (name "(PCINT9/XTAL2)PB1") (type BiDi)) + (pin (num 4) (name "(PCINT11/dW/~RESET~)PB3") (type BiDi)) + (pin (num 5) (name "(PCINT10/CKOUT/OC0A/INT0)PB2") (type BiDi)) + (pin (num 6) (name "(PCINT7/ICP/OC0B/ADC7)PA7") (type BiDi)) + (pin (num 7) (name "(PCINT6/SDA/DI/MOSI/OC1A/ADC6)PA6") (type BiDi)) + (pin (num 8) (name "(PCINT5/DO/MISO/OC1B/ADC5)PA5") (type BiDi)) + (pin (num 9) (name "(PCINT4/USCK/SCL/T1/ADC4)PA4") (type BiDi)) + (pin (num 10) (name "(PCINT3/T0/ADC3)PA3") (type BiDi)) + (pin (num 11) (name "(PCINT2/AIN1/ADC2)PA2") (type BiDi)) + (pin (num 12) (name "(PCINT1/AIN0/ADC1)PA1") (type BiDi)) + (pin (num 13) (name "(PCINT0/AREF/ADC0)PA0") (type BiDi)) + (pin (num 14) (name GND) (type power_in)))) + (libpart (lib conn) (part CONN_01X01) + (description "Connector 01x01") + (footprints + (fp Pin_Header_Straight_1X01) + (fp Pin_Header_Angled_1X01) + (fp Socket_Strip_Straight_1X01) + (fp Socket_Strip_Angled_1X01)) + (fields + (field (name Reference) P) + (field (name Value) CONN_01X01)) + (pins + (pin (num 1) (name P1) (type passive)))) + (libpart (lib conn) (part CONN_01X02) + (description "Connector 01x02") + (footprints + (fp Pin_Header_Straight_1X02) + (fp Pin_Header_Angled_1X02) + (fp Socket_Strip_Straight_1X02) + (fp Socket_Strip_Angled_1X02)) + (fields + (field (name Reference) P) + (field (name Value) CONN_01X02)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)))) + (libpart (lib conn) (part CONN_01X04) + (description "Connector 01x04") + (footprints + (fp Pin_Header_Straight_1X04) + (fp Pin_Header_Angled_1X04) + (fp Socket_Strip_Straight_1X04) + (fp Socket_Strip_Angled_1X04)) + (fields + (field (name Reference) P) + (field (name Value) CONN_01X04)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)))) + (libpart (lib conn) (part CONN_02X04) + (description "Connector 02x04") + (footprints + (fp Pin_Header_Straight_2X04) + (fp Pin_Header_Angled_2X04) + (fp Socket_Strip_Straight_2X04) + (fp Socket_Strip_Angled_2X04)) + (fields + (field (name Reference) P) + (field (name Value) CONN_02X04)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)) + (pin (num 5) (name P5) (type passive)) + (pin (num 6) (name P6) (type passive)) + (pin (num 7) (name P7) (type passive)) + (pin (num 8) (name P8) (type passive)))) + (libpart (lib conn) (part CONN_02X20) + (description "Connector 02x20") + (footprints + (fp Pin_Header_Straight_2X20) + (fp Pin_Header_Angled_2X20) + (fp Socket_Strip_Straight_2X20) + (fp Socket_Strip_Angled_2X20)) + (fields + (field (name Reference) P) + (field (name Value) CONN_02X20)) + (pins + (pin (num 1) (name P1) (type passive)) + (pin (num 2) (name P2) (type passive)) + (pin (num 3) (name P3) (type passive)) + (pin (num 4) (name P4) (type passive)) + (pin (num 5) (name P5) (type passive)) + (pin (num 6) (name P6) (type passive)) + (pin (num 7) (name P7) (type passive)) + (pin (num 8) (name P8) (type passive)) + (pin (num 9) (name P9) (type passive)) + (pin (num 10) (name P10) (type passive)) + (pin (num 11) (name P11) (type passive)) + (pin (num 12) (name P12) (type passive)) + (pin (num 13) (name P13) (type passive)) + (pin (num 14) (name P14) (type passive)) + (pin (num 15) (name P15) (type passive)) + (pin (num 16) (name P16) (type passive)) + (pin (num 17) (name P17) (type passive)) + (pin (num 18) (name P18) (type passive)) + (pin (num 19) (name P19) (type passive)) + (pin (num 20) (name P20) (type passive)) + (pin (num 21) (name P21) (type passive)) + (pin (num 22) (name P22) (type passive)) + (pin (num 23) (name P23) (type passive)) + (pin (num 24) (name P24) (type passive)) + (pin (num 25) (name P25) (type passive)) + (pin (num 26) (name P26) (type passive)) + (pin (num 27) (name P27) (type passive)) + (pin (num 28) (name P28) (type passive)) + (pin (num 29) (name P29) (type passive)) + (pin (num 30) (name P30) (type passive)) + (pin (num 31) (name P31) (type passive)) + (pin (num 32) (name P32) (type passive)) + (pin (num 33) (name P33) (type passive)) + (pin (num 34) (name P34) (type passive)) + (pin (num 35) (name P35) (type passive)) + (pin (num 36) (name P36) (type passive)) + (pin (num 37) (name P37) (type passive)) + (pin (num 38) (name P38) (type passive)) + (pin (num 39) (name P39) (type passive)) + (pin (num 40) (name P40) (type passive)))) + (libpart (lib device) (part CP) + (description "Polarised capacitor") + (footprints + (fp CP*) + (fp Elko*) + (fp TantalC*) + (fp C*elec) + (fp c_elec*) + (fp SMD*_Pol)) + (fields + (field (name Reference) C) + (field (name Value) CP)) + (pins + (pin (num 1) (name ~) (type passive)) + (pin (num 2) (name ~) (type passive)))) + (libpart (lib device) (part R) + (description Resistor) + (footprints + (fp R_*) + (fp Resistor_*)) + (fields + (field (name Reference) R) + (field (name Value) R)) + (pins + (pin (num 1) (name ~) (type passive)) + (pin (num 2) (name ~) (type passive))))) + (libraries + (library (logical device) + (uri /usr/share/kicad/library/device.lib)) + (library (logical conn) + (uri /usr/share/kicad/library/conn.lib)) + (library (logical atmel) + (uri /usr/share/kicad/library/atmel.lib))) + (nets + (net (code 1) (name MISO) + (node (ref IC1) (pin 8)) + (node (ref P3) (pin 7)) + (node (ref P1) (pin 21))) + (net (code 2) (name MOSI) + (node (ref P3) (pin 6)) + (node (ref IC1) (pin 7)) + (node (ref P1) (pin 19))) + (net (code 3) (name Tiny-RESET) + (node (ref R10) (pin 2)) + (node (ref P1) (pin 15)) + (node (ref IC1) (pin 4))) + (net (code 4) (name /NRF-INT) + (node (ref P3) (pin 8))) + (net (code 5) (name SCK) + (node (ref P3) (pin 5)) + (node (ref IC1) (pin 9)) + (node (ref P1) (pin 23))) + (net (code 6) (name CE) + (node (ref P3) (pin 3)) + (node (ref P1) (pin 18))) + (net (code 7) (name SS1) + (node (ref P1) (pin 24)) + (node (ref IC1) (pin 5))) + (net (code 8) (name +3V3) + (node (ref C3) (pin 2)) + (node (ref R10) (pin 1)) + (node (ref IC1) (pin 1)) + (node (ref P3) (pin 1)) + (node (ref P1) (pin 17))) + (net (code 9) (name SS0) + (node (ref P3) (pin 4)) + (node (ref P1) (pin 22))) + (net (code 10) (name "Net-(P1-Pad32)") + (node (ref P1) (pin 32))) + (net (code 11) (name "Net-(P1-Pad25)") + (node (ref P1) (pin 25))) + (net (code 12) (name "Net-(P1-Pad34)") + (node (ref P1) (pin 34))) + (net (code 13) (name "Net-(P1-Pad14)") + (node (ref P1) (pin 14))) + (net (code 14) (name "Net-(P1-Pad33)") + (node (ref P1) (pin 33))) + (net (code 15) (name "Net-(P1-Pad13)") + (node (ref P1) (pin 13))) + (net (code 16) (name "Net-(P1-Pad35)") + (node (ref P1) (pin 35))) + (net (code 17) (name "Net-(P1-Pad12)") + (node (ref P1) (pin 12))) + (net (code 18) (name "Net-(P1-Pad31)") + (node (ref P1) (pin 31))) + (net (code 19) (name "Net-(P1-Pad11)") + (node (ref P1) (pin 11))) + (net (code 20) (name "Net-(P1-Pad40)") + (node (ref P1) (pin 40))) + (net (code 21) (name "Net-(P1-Pad30)") + (node (ref P1) (pin 30))) + (net (code 22) (name "Net-(P1-Pad28)") + (node (ref P1) (pin 28))) + (net (code 23) (name "Net-(P1-Pad39)") + (node (ref P1) (pin 39))) + (net (code 24) (name "Net-(P1-Pad29)") + (node (ref P1) (pin 29))) + (net (code 25) (name "Net-(P1-Pad38)") + (node (ref P1) (pin 38))) + (net (code 26) (name "Net-(P1-Pad37)") + (node (ref P1) (pin 37))) + (net (code 27) (name "Net-(P1-Pad27)") + (node (ref P1) (pin 27))) + (net (code 28) (name "Net-(P1-Pad36)") + (node (ref P1) (pin 36))) + (net (code 29) (name "Net-(P1-Pad26)") + (node (ref P1) (pin 26))) + (net (code 30) (name "Net-(P1-Pad16)") + (node (ref P1) (pin 16))) + (net (code 31) (name +5V) + (node (ref P7) (pin 1)) + (node (ref P4) (pin 1)) + (node (ref C4) (pin 1)) + (node (ref P1) (pin 2)) + (node (ref P1) (pin 4)) + (node (ref P2) (pin 1))) + (net (code 32) (name GND) + (node (ref C4) (pin 2)) + (node (ref P1) (pin 6)) + (node (ref P2) (pin 2)) + (node (ref P4) (pin 2)) + (node (ref P6) (pin 4)) + (node (ref P7) (pin 4)) + (node (ref C3) (pin 1)) + (node (ref P1) (pin 20)) + (node (ref IC1) (pin 14)) + (node (ref P3) (pin 2))) + (net (code 33) (name /ADC3) + (node (ref IC1) (pin 10)) + (node (ref P6) (pin 3))) + (net (code 34) (name /ADC2) + (node (ref P6) (pin 2)) + (node (ref IC1) (pin 11))) + (net (code 35) (name /ADC1) + (node (ref P6) (pin 1)) + (node (ref IC1) (pin 12))) + (net (code 36) (name "Net-(P1-Pad1)") + (node (ref P1) (pin 1))) + (net (code 37) (name /ANT) + (node (ref P4) (pin 4)) + (node (ref P5) (pin 1))) + (net (code 38) (name TX) + (node (ref IC1) (pin 3)) + (node (ref P1) (pin 8))) + (net (code 39) (name RX) + (node (ref IC1) (pin 2)) + (node (ref P1) (pin 10))) + (net (code 40) (name "Net-(P1-Pad9)") + (node (ref P1) (pin 9))) + (net (code 41) (name "Net-(P1-Pad7)") + (node (ref P1) (pin 7))) + (net (code 42) (name "Net-(P1-Pad5)") + (node (ref P1) (pin 5))) + (net (code 43) (name "Net-(P1-Pad3)") + (node (ref P1) (pin 3))) + (net (code 44) (name "Net-(P7-Pad2)") + (node (ref P7) (pin 2))) + (net (code 45) (name /RF433-IN) + (node (ref IC1) (pin 6)) + (node (ref P7) (pin 3))) + (net (code 46) (name /RF433-OUT) + (node (ref IC1) (pin 13)) + (node (ref P4) (pin 3))))) \ No newline at end of file diff --git a/domopi.pro b/domopi.pro new file mode 100644 index 0000000..9a9ced9 --- /dev/null +++ b/domopi.pro @@ -0,0 +1,61 @@ +update=mer. 30 sept. 2015 14:42:03 CEST +version=1 +last_client=kicad +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[general] +version=1 +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=microcontrollers +LibName13=dsp +LibName14=microchip +LibName15=analog_switches +LibName16=motorola +LibName17=texas +LibName18=intel +LibName19=audio +LibName20=interface +LibName21=digital-audio +LibName22=philips +LibName23=display +LibName24=cypress +LibName25=siliconi +LibName26=opto +LibName27=atmel +LibName28=contrib +LibName29=valves +LibName30=/home/arnaud/kicad/libs/lm3940it-3 diff --git a/domopi.sch b/domopi.sch new file mode 100644 index 0000000..12daee7 --- /dev/null +++ b/domopi.sch @@ -0,0 +1,651 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:lm3940it-3 +LIBS:domopi-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L ATTINY84A-P IC1 +U 1 1 560BE23A +P 7000 2000 +F 0 "IC1" H 6150 2750 40 0000 C CNN +F 1 "ATTINY84A-P" H 7700 1250 40 0000 C CNN +F 2 "Housings_DIP:DIP-14_W7.62mm" H 7000 1800 35 0000 C CIN +F 3 "" H 7000 2000 60 0000 C CNN + 1 7000 2000 + 1 0 0 -1 +$EndComp +$Comp +L CONN_02X04 P3 +U 1 1 560BE537 +P 5400 4050 +F 0 "P3" H 5400 4300 50 0000 C CNN +F 1 "nRF24L01P" H 5400 3800 50 0000 C CNN +F 2 "Pin_Headers:Pin_Header_Straight_2x04" H 5400 2850 60 0001 C CNN +F 3 "" H 5400 2850 60 0000 C CNN + 1 5400 4050 + 1 0 0 -1 +$EndComp +Text Label 4750 3900 0 60 ~ 0 +NRF-GND +Text Label 5650 3900 0 60 ~ 0 +NRF-VCC +NoConn ~ 6100 4200 +Text Label 4300 4000 0 60 ~ 0 +NRF-CE +Text Label 5650 4000 0 60 ~ 0 +NRF-CSN +Text Label 4750 4100 0 60 ~ 0 +NRF-SCK +Text Label 5650 4100 0 60 ~ 0 +NRF-MOSI +Text Label 4750 4200 0 60 ~ 0 +NRF-MISO +Text Label 5650 4200 0 60 ~ 0 +NRF-INT +$Comp +L +5V #PWR01 +U 1 1 560BEDEC +P 3400 1850 +F 0 "#PWR01" H 3400 1700 50 0001 C CNN +F 1 "+5V" H 3400 1990 50 0000 C CNN +F 2 "" H 3400 1850 60 0000 C CNN +F 3 "" H 3400 1850 60 0000 C CNN + 1 3400 1850 + 1 0 0 -1 +$EndComp +$Comp +L +3.3V #PWR02 +U 1 1 560BEE81 +P 5500 1100 +F 0 "#PWR02" H 5500 950 50 0001 C CNN +F 1 "+3.3V" H 5500 1240 50 0000 C CNN +F 2 "" H 5500 1100 60 0000 C CNN +F 3 "" H 5500 1100 60 0000 C CNN + 1 5500 1100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR03 +U 1 1 560BEFB1 +P 5500 2850 +F 0 "#PWR03" H 5500 2600 50 0001 C CNN +F 1 "GND" H 5500 2700 50 0000 C CNN +F 2 "" H 5500 2850 60 0000 C CNN +F 3 "" H 5500 2850 60 0000 C CNN + 1 5500 2850 + 1 0 0 -1 +$EndComp +Text GLabel 2400 2850 0 60 Output ~ 0 +MOSI +Text GLabel 2400 2650 0 60 Output ~ 0 +Tiny-RESET +Text GLabel 2400 2950 0 60 Input ~ 0 +MISO +Text GLabel 2400 3050 0 60 Output ~ 0 +SCK +$Comp +L GND #PWR04 +U 1 1 560C03CA +P 3600 1450 +F 0 "#PWR04" H 3600 1200 50 0001 C CNN +F 1 "GND" H 3600 1300 50 0000 C CNN +F 2 "" H 3600 1450 60 0000 C CNN +F 3 "" H 3600 1450 60 0000 C CNN + 1 3600 1450 + -1 0 0 1 +$EndComp +Text GLabel 3500 2950 2 60 Output ~ 0 +SS0 +Text GLabel 3500 3050 2 60 Output ~ 0 +SS1 +Text GLabel 3500 2750 2 60 Output ~ 0 +CE +$Comp +L GND #PWR05 +U 1 1 560C154F +P 3400 4000 +F 0 "#PWR05" H 3400 3750 50 0001 C CNN +F 1 "GND" H 3400 3850 50 0000 C CNN +F 2 "" H 3400 4000 60 0000 C CNN +F 3 "" H 3400 4000 60 0000 C CNN + 1 3400 4000 + 1 0 0 -1 +$EndComp +Text GLabel 4300 4000 0 60 Input ~ 0 +CE +$Comp +L CP C3 +U 1 1 560C23BB +P 5400 3550 +F 0 "C3" H 5425 3650 50 0000 L CNN +F 1 "10u" H 5425 3450 50 0000 L CNN +F 2 "Capacitors_Elko_ThroughHole:Elko_vert_11.2x6.3mm_RM2.5" H 5438 3400 30 0001 C CNN +F 3 "" H 5400 3550 60 0000 C CNN + 1 5400 3550 + 0 1 1 0 +$EndComp +$Comp +L +3.3V #PWR06 +U 1 1 560C44FC +P 4750 3600 +F 0 "#PWR06" H 4750 3450 50 0001 C CNN +F 1 "+3.3V" H 4750 3740 50 0000 C CNN +F 2 "" H 4750 3600 60 0000 C CNN +F 3 "" H 4750 3600 60 0000 C CNN + 1 4750 3600 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR07 +U 1 1 560C46E1 +P 6200 3700 +F 0 "#PWR07" H 6200 3450 50 0001 C CNN +F 1 "GND" H 6200 3550 50 0000 C CNN +F 2 "" H 6200 3700 60 0000 C CNN +F 3 "" H 6200 3700 60 0000 C CNN + 1 6200 3700 + -1 0 0 1 +$EndComp +Text GLabel 4300 4200 0 60 Input ~ 0 +SCK +Text GLabel 4750 4200 0 60 Output ~ 0 +MISO +Text GLabel 6400 4100 2 60 Input ~ 0 +MOSI +Text GLabel 6100 4000 2 60 Input ~ 0 +SS0 +Text GLabel 3650 2250 2 60 Output ~ 0 +TX +Text GLabel 3800 2350 2 60 Input ~ 0 +RX +Text GLabel 8450 2400 2 60 Input ~ 0 +TX +Text GLabel 8450 2300 2 60 Output ~ 0 +RX +Text GLabel 9800 2600 2 60 Input ~ 0 +Tiny-RESET +$Comp +L +3.3V #PWR08 +U 1 1 560CAD22 +P 9350 1950 +F 0 "#PWR08" H 9350 1800 50 0001 C CNN +F 1 "+3.3V" H 9350 2090 50 0000 C CNN +F 2 "" H 9350 1950 60 0000 C CNN +F 3 "" H 9350 1950 60 0000 C CNN + 1 9350 1950 + 1 0 0 -1 +$EndComp +$Comp +L R R10 +U 1 1 560CAD51 +P 9350 2300 +F 0 "R10" V 9430 2300 50 0000 C CNN +F 1 "4.7k" V 9350 2300 50 0000 C CNN +F 2 "Resistors_ThroughHole:Resistor_Vertical_RM5mm" V 9280 2300 30 0001 C CNN +F 3 "" H 9350 2300 30 0000 C CNN + 1 9350 2300 + 1 0 0 -1 +$EndComp +Text GLabel 8650 2000 2 60 Input ~ 0 +MOSI +Text GLabel 8750 1900 2 60 Output ~ 0 +MISO +Text GLabel 8650 1800 2 60 Input ~ 0 +SCK +Text GLabel 8450 2500 2 60 Input ~ 0 +SS1 +Text Label 8600 1400 2 60 ~ 0 +RF433-OUT +Text Label 8500 2100 2 60 ~ 0 +RF433-IN +$Comp +L CONN_01X04 P6 +U 1 1 560CF763 +P 9850 1650 +F 0 "P6" H 9850 1850 50 0000 C CNN +F 1 "Sensors" V 9950 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